From 36c4134a26063248a2ef47f5ac8defe50d9476b1 Mon Sep 17 00:00:00 2001
From: Uri Shaked
Date: Wed, 9 Dec 2020 00:51:13 +0200
Subject: refactor: central interrupt handling #38

---
 src/peripherals/spi.spec.ts | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/peripherals/spi.spec.ts')

diff --git a/src/peripherals/spi.spec.ts b/src/peripherals/spi.spec.ts
index 1bb099f..8e11b94 100644
--- a/src/peripherals/spi.spec.ts
+++ b/src/peripherals/spi.spec.ts
@@ -177,6 +177,7 @@ describe('SPI', () => {
     cpu.writeData(SPCR, SPE | MSTR);
     cpu.writeData(SPDR, 0x50);
     spi.tick();
+    cpu.tick();
     expect(cpu.readData(SPSR) & WCOL).toEqual(0);
 
     cpu.writeData(SPDR, 0x51);
@@ -194,11 +195,13 @@ describe('SPI', () => {
     // At this point, write shouldn't be complete yet
     cpu.cycles += 10;
     spi.tick();
+    cpu.tick();
     expect(cpu.pc).toEqual(0);
 
     // 100 cycles later, it should (8 bits * 8 cycles per bit = 64).
     cpu.cycles += 100;
     spi.tick();
+    cpu.tick();
     expect(cpu.data[SPSR] & SPIF).toEqual(0);
     expect(cpu.pc).toEqual(0x22); // SPI Ready interrupt
   });
@@ -213,10 +216,12 @@ describe('SPI', () => {
 
     cpu.cycles = 10;
     spi.tick();
+    cpu.tick();
     expect(cpu.readData(SPDR)).toEqual(0);
 
     cpu.cycles = 32; // 4 cycles per bit * 8 bits = 32
     spi.tick();
+    cpu.tick();
     expect(cpu.readData(SPDR)).toEqual(0x88);
   });
 });
-- 
cgit v1.2.3


From 9c1288f18889ae3bd10869a9f6ebc53defa3024b Mon Sep 17 00:00:00 2001
From: Uri Shaked
Date: Wed, 9 Dec 2020 15:46:53 +0200
Subject: perf!: centeral timekeeping

This should improve performance, especially when running simulations with
multiple peripherals. For instance, the demo project now runs at ~322%,
up from ~185% in AVR8js 0.13.1.

BREAKING CHANGE: `tick()` methods were removed from individual peripherals.
You now need to call `cpu.tick()` instead.
---
 src/peripherals/spi.spec.ts | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

(limited to 'src/peripherals/spi.spec.ts')

diff --git a/src/peripherals/spi.spec.ts b/src/peripherals/spi.spec.ts
index 8e11b94..635e657 100644
--- a/src/peripherals/spi.spec.ts
+++ b/src/peripherals/spi.spec.ts
@@ -160,7 +160,7 @@ describe('SPI', () => {
       return 0x5b; // we copy this byte to
     };
 
-    const runner = new TestProgramRunner(cpu, spi);
+    const runner = new TestProgramRunner(cpu);
     runner.runToBreak();
 
     // 16 cycles per clock * 8 bits = 128
@@ -172,11 +172,10 @@ describe('SPI', () => {
 
   it('should set the WCOL bit in SPSR if writing to SPDR while SPI is already transmitting', () => {
     const cpu = new CPU(new Uint16Array(1024));
-    const spi = new AVRSPI(cpu, spiConfig, FREQ_16MHZ);
+    new AVRSPI(cpu, spiConfig, FREQ_16MHZ);
 
     cpu.writeData(SPCR, SPE | MSTR);
     cpu.writeData(SPDR, 0x50);
-    spi.tick();
     cpu.tick();
     expect(cpu.readData(SPSR) & WCOL).toEqual(0);
 
@@ -186,7 +185,7 @@ describe('SPI', () => {
 
   it('should clear the SPIF bit and fire an interrupt when SPI transfer completes', () => {
     const cpu = new CPU(new Uint16Array(1024));
-    const spi = new AVRSPI(cpu, spiConfig, FREQ_16MHZ);
+    new AVRSPI(cpu, spiConfig, FREQ_16MHZ);
 
     cpu.writeData(SPCR, SPE | SPIE | MSTR);
     cpu.writeData(SPDR, 0x50);
@@ -194,13 +193,11 @@ describe('SPI', () => {
 
     // At this point, write shouldn't be complete yet
     cpu.cycles += 10;
-    spi.tick();
     cpu.tick();
     expect(cpu.pc).toEqual(0);
 
     // 100 cycles later, it should (8 bits * 8 cycles per bit = 64).
     cpu.cycles += 100;
-    spi.tick();
     cpu.tick();
     expect(cpu.data[SPSR] & SPIF).toEqual(0);
     expect(cpu.pc).toEqual(0x22); // SPI Ready interrupt
@@ -215,12 +212,10 @@ describe('SPI', () => {
     cpu.writeData(SPDR, 0x8f);
 
     cpu.cycles = 10;
-    spi.tick();
     cpu.tick();
     expect(cpu.readData(SPDR)).toEqual(0);
 
     cpu.cycles = 32; // 4 cycles per bit * 8 bits = 32
-    spi.tick();
     cpu.tick();
     expect(cpu.readData(SPDR)).toEqual(0x88);
   });
-- 
cgit v1.2.3