From 619652de465c0f3c73d867de3ec51c21f612b082 Mon Sep 17 00:00:00 2001
From: Uri Shaked
Date: Sat, 4 Apr 2020 16:22:32 +0300
Subject: feat(timer): implement 16-bit timers

e.g. Timer/Counter1 on ATmega328
---
 src/peripherals/timer.spec.ts | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

(limited to 'src/peripherals/timer.spec.ts')

diff --git a/src/peripherals/timer.spec.ts b/src/peripherals/timer.spec.ts
index adcef04..7750f26 100644
--- a/src/peripherals/timer.spec.ts
+++ b/src/peripherals/timer.spec.ts
@@ -1,5 +1,5 @@
 import { CPU } from '../cpu/cpu';
-import { AVRTimer, timer0Config, timer2Config } from './timer';
+import { AVRTimer, timer0Config, timer1Config, timer2Config } from './timer';
 
 describe('timer', () => {
   let cpu: CPU;
@@ -201,4 +201,21 @@ describe('timer', () => {
     timer.tick();
     expect(cpu.data[0xb2]).toEqual(2); // TCNT2 should be 2
   });
+
+  describe('16 bit timers', () => {
+    it('should set OCF0A flag when timer equals OCRA (16 bit mode)', () => {
+      const timer = new AVRTimer(cpu, timer1Config);
+      cpu.writeData(0x84, 0xee); // TCNT1 <- 0x10ee
+      cpu.writeData(0x85, 0x10); // ...
+      cpu.writeData(0x88, 0xef); // OCR1A <- 0x10ef
+      cpu.writeData(0x89, 0x10); // ...
+      cpu.writeData(0x80, 0x0); // WGM1 <- 0 (Normal)
+      cpu.writeData(0x81, 0x1); // TCCR1B.CS <- 1
+      cpu.cycles = 1;
+      timer.tick();
+      expect(cpu.data[0x36]).toEqual(2); // TIFR0 should have OCF0A bit on
+      expect(cpu.pc).toEqual(0);
+      expect(cpu.cycles).toEqual(1);
+    });
+  });
 });
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