From 77afa2308ed969a9583149646d05e26716f672d8 Mon Sep 17 00:00:00 2001
From: Uri Shaked
Date: Thu, 15 Jul 2021 17:53:05 +0300
Subject: feat(usart): add configuration change event

also add `txEnable` and `rxEnable` properties
---
 src/peripherals/usart.spec.ts | 56 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

(limited to 'src/peripherals/usart.spec.ts')

diff --git a/src/peripherals/usart.spec.ts b/src/peripherals/usart.spec.ts
index f92ea00..8dbd5ce 100644
--- a/src/peripherals/usart.spec.ts
+++ b/src/peripherals/usart.spec.ts
@@ -53,6 +53,24 @@ describe('USART', () => {
     expect(usart.baudRate).toEqual(2400);
   });
 
+  it('should call onConfigurationChange when the baudRate changes', () => {
+    const cpu = new CPU(new Uint16Array(1024));
+    const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
+    const onConfigurationChange = jest.fn();
+    usart.onConfigurationChange = onConfigurationChange;
+
+    cpu.writeData(UBRR0H, 0);
+    expect(onConfigurationChange).toHaveBeenCalled();
+
+    onConfigurationChange.mockClear();
+    cpu.writeData(UBRR0L, 5);
+    expect(onConfigurationChange).toHaveBeenCalled();
+
+    onConfigurationChange.mockClear();
+    cpu.writeData(UCSR0A, U2X0);
+    expect(onConfigurationChange).toHaveBeenCalled();
+  });
+
   describe('bitsPerChar', () => {
     it('should return 5-bits per byte when UCSZ = 0', () => {
       const cpu = new CPU(new Uint16Array(1024));
@@ -89,6 +107,24 @@ describe('USART', () => {
       cpu.writeData(UCSR0B, UCSZ2);
       expect(usart.bitsPerChar).toEqual(9);
     });
+
+    it('should call onConfigurationChange when bitsPerChar change', () => {
+      const cpu = new CPU(new Uint16Array(1024));
+      const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
+      const onConfigurationChange = jest.fn();
+      usart.onConfigurationChange = onConfigurationChange;
+
+      cpu.writeData(UCSR0C, UCSZ0 | UCSZ1);
+      expect(onConfigurationChange).toHaveBeenCalled();
+
+      onConfigurationChange.mockClear();
+      cpu.writeData(UCSR0B, UCSZ2);
+      expect(onConfigurationChange).toHaveBeenCalled();
+
+      onConfigurationChange.mockClear();
+      cpu.writeData(UCSR0B, UCSZ2);
+      expect(onConfigurationChange).not.toHaveBeenCalled();
+    });
   });
 
   describe('stopBits', () => {
@@ -145,6 +181,26 @@ describe('USART', () => {
     expect(usart.onByteTransmit).toHaveBeenCalledWith(0x61);
   });
 
+  describe('txEnable/rxEnable', () => {
+    it('txEnable should equal true when the transitter is enabled', () => {
+      const cpu = new CPU(new Uint16Array(1024));
+      const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
+      usart.onByteTransmit = jest.fn();
+      expect(usart.txEnable).toEqual(false);
+      cpu.writeData(UCSR0B, TXEN);
+      expect(usart.txEnable).toEqual(true);
+    });
+
+    it('rxEnable should equal true when the transitter is enabled', () => {
+      const cpu = new CPU(new Uint16Array(1024));
+      const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
+      usart.onByteTransmit = jest.fn();
+      expect(usart.rxEnable).toEqual(false);
+      cpu.writeData(UCSR0B, RXEN);
+      expect(usart.rxEnable).toEqual(true);
+    });
+  });
+
   describe('tick()', () => {
     it('should trigger data register empty interrupt if UDRE is set', () => {
       const cpu = new CPU(new Uint16Array(1024));
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