1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
|
import { CPU } from '../cpu/cpu';
import { avrInstruction } from '../cpu/instruction';
import { assemble } from '../utils/assembler';
import { AVRTimer, timer0Config, timer1Config, timer2Config } from './timer';
describe('timer', () => {
let cpu: CPU;
beforeEach(() => {
cpu = new CPU(new Uint16Array(0x1000));
});
function loadProgram(...instructions: string[]) {
const { bytes, errors } = assemble(instructions.join('\n'));
if (errors.length) {
throw new Error('Assembly failed: ' + errors);
}
cpu.progBytes.set(bytes, 0);
}
it('should update timer every tick when prescaler is 1', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.data[0x45] = 0x1; // TCCR0B.CS <- 1
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x46]).toEqual(1); // TCNT should be 1
});
it('should update timer every 64 ticks when prescaler is 3', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.data[0x45] = 0x3; // TCCR0B.CS <- 3
cpu.cycles = 64;
timer.tick();
expect(cpu.data[0x46]).toEqual(1); // TCNT should be 1
});
it('should not update timer if it has been disabled', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.data[0x45] = 0; // TCCR0B.CS <- 0
cpu.cycles = 100000;
timer.tick();
expect(cpu.data[0x46]).toEqual(0); // TCNT should stay 0
});
it('should set TOV if timer overflows', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.data[0x46] = 0xff; // TCNT0 <- 0xff
cpu.data[0x45] = 0x1; // TCCR0B.CS <- 1
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x46]).toEqual(0); // TCNT should be 0
expect(cpu.data[0x35]).toEqual(1); // TOV bit in TIFR
});
it('should set TOV if timer overflows in PWM Phase Correct mode', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.data[0x46] = 0xff; // TCNT0 <- 0xff
cpu.writeData(0x47, 0x7f); // OCRA <- 0x7f
cpu.writeData(0x44, 0x1); // WGM0 <- 1 (PWM, Phase Correct)
cpu.data[0x45] = 0x1; // TCCR0B.CS <- 1
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x46]).toEqual(0); // TCNT should be 0
expect(cpu.data[0x35]).toEqual(1); // TOV bit in TIFR
});
it('should set TOV if timer overflows in FAST PWM mode', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.data[0x46] = 0xff; // TCNT0 <- 0xff
cpu.writeData(0x47, 0x7f); // OCRA <- 0x7f
cpu.writeData(0x44, 0x3); // WGM0 <- 3 (FAST PWM)
cpu.data[0x45] = 0x1; // TCCR0B.CS <- 1
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x46]).toEqual(0); // TCNT should be 0
expect(cpu.data[0x35]).toEqual(1); // TOV bit in TIFR
});
it('should generate an overflow interrupt if timer overflows and interrupts enabled', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.data[0x46] = 0xff; // TCNT0 <- 0xff
cpu.data[0x45] = 0x1; // TCCR0B.CS <- 1
cpu.data[0x6e] = 0x1; // TIMSK0: TOIE0
cpu.data[95] = 0x80; // SREG: I-------
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x46]).toEqual(0); // TCNT should be 0
expect(cpu.data[0x35]).toEqual(0); // TOV bit in TIFR should be clear
expect(cpu.pc).toEqual(0x20);
expect(cpu.cycles).toEqual(3);
});
it('should not generate an overflow interrupt when global interrupts disabled', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.data[0x46] = 0xff; // TCNT0 <- 0xff
cpu.data[0x45] = 0x1; // TCCR0B.CS <- 1
cpu.data[0x6e] = 0x1; // TIMSK0: TOIE0
cpu.data[95] = 0x0; // SREG: --------
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x35]).toEqual(1); // TOV bit in TIFR should be set
expect(cpu.pc).toEqual(0);
expect(cpu.cycles).toEqual(1);
});
it('should not generate an overflow interrupt when TOIE0 is clear', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.data[0x46] = 0xff; // TCNT0 <- 0xff
cpu.data[0x45] = 0x1; // TCCR0B.CS <- 1
cpu.data[0x6e] = 0; // TIMSK0: clear
cpu.data[95] = 0x80; // SREG: I-------
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x35]).toEqual(1); // TOV bit in TIFR should be set
expect(cpu.pc).toEqual(0);
expect(cpu.cycles).toEqual(1);
});
it('should set OCF0A flag when timer equals OCRA', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.writeData(0x46, 0x10); // TCNT0 <- 0x10
timer.tick();
cpu.writeData(0x47, 0x11); // OCR0A <- 0x11
cpu.writeData(0x44, 0x0); // WGM0 <- 0 (Normal)
cpu.writeData(0x45, 0x1); // TCCR0B.CS <- 1
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x35]).toEqual(2); // TIFR0 should have OCF0A bit on
expect(cpu.pc).toEqual(0);
expect(cpu.cycles).toEqual(1);
});
it('should clear the timer in CTC mode if it equals to OCRA', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.writeData(0x46, 0x10); // TCNT0 <- 0x10
timer.tick();
cpu.writeData(0x47, 0x11); // OCR0A <- 0x11
cpu.writeData(0x44, 0x2); // WGM0 <- 2 (CTC)
cpu.writeData(0x45, 0x1); // TCCR0B.CS <- 1
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x46]).toEqual(0); // TCNT should be 0
expect(cpu.pc).toEqual(0);
expect(cpu.cycles).toEqual(1);
});
it('should set OCF0B flag when timer equals OCRB', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.writeData(0x46, 0x10); // TCNT0 <- 0x50
timer.tick();
cpu.writeData(0x48, 0x11); // OCR0B <- 0x51
cpu.writeData(0x44, 0x0); // WGM0 <- 0 (Normal)
cpu.writeData(0x45, 0x1); // TCCR0B.CS <- 1
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x35]).toEqual(4); // TIFR0 should have OCF0B bit on
expect(cpu.pc).toEqual(0);
expect(cpu.cycles).toEqual(1);
});
it('should generate Timer Compare A interrupt when TCNT0 == TCNTA', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.writeData(0x46, 0x20); // TCNT0 <- 0x20
timer.tick();
cpu.writeData(0x47, 0x21); // OCR0A <- 0x21
cpu.writeData(0x45, 0x1); // TCCR0B.CS <- 1
cpu.writeData(0x6e, 0x2); // TIMSK0: OCIEA
cpu.writeData(95, 0x80); // SREG: I-------
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x46]).toEqual(0x21); // TCNT should be 0x21
expect(cpu.data[0x35]).toEqual(0); // OCFA bit in TIFR should be clear
expect(cpu.pc).toEqual(0x1c);
expect(cpu.cycles).toEqual(3);
});
it('should not generate Timer Compare A interrupt when OCIEA is disabled', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.writeData(0x46, 0x20); // TCNT0 <- 0x20
timer.tick();
cpu.writeData(0x47, 0x21); // OCR0A <- 0x21
cpu.writeData(0x45, 0x1); // TCCR0B.CS <- 1
cpu.writeData(0x6e, 0); // TIMSK0
cpu.writeData(95, 0x80); // SREG: I-------
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x46]).toEqual(0x21); // TCNT should be 0x21
expect(cpu.pc).toEqual(0);
expect(cpu.cycles).toEqual(1);
});
it('should generate Timer Compare B interrupt when TCNT0 == TCNTB', () => {
const timer = new AVRTimer(cpu, timer0Config);
cpu.writeData(0x46, 0x20); // TCNT0 <- 0x20
timer.tick();
cpu.writeData(0x48, 0x21); // OCR0B <- 0x21
cpu.writeData(0x45, 0x1); // TCCR0B.CS <- 1
cpu.writeData(0x6e, 0x4); // TIMSK0: OCIEB
cpu.writeData(95, 0x80); // SREG: I-------
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x46]).toEqual(0x21); // TCNT should be 0x21
expect(cpu.data[0x35]).toEqual(0); // OCFB bit in TIFR should be clear
expect(cpu.pc).toEqual(0x1e);
expect(cpu.cycles).toEqual(3);
});
it('should not increment TCNT on the same cycle of TCNT write (issue #36)', () => {
// At the end of this short program, R17 should contain 0x31. Verified against
// a physical ATmega328p.
const program = [
'LDI r16, 0x1', // TCCR0B = 1 << CS00;
'OUT 0x25, r16',
'LDI r16, 0x30', // TCNT <- 0x30
'OUT 0x26, r16',
'NOP',
'IN r17, 0x26' // r17 <- TCNT
];
loadProgram(...program);
const timer = new AVRTimer(cpu, timer0Config);
for (let i = 0; i < program.length; i++) {
avrInstruction(cpu);
timer.tick();
}
expect(cpu.data[17]).toEqual(0x31); // r1 should be 0x31
});
it('timer2 should count every 256 ticks when prescaler is 6 (issue #5)', () => {
const timer = new AVRTimer(cpu, timer2Config);
cpu.data[0xb1] = 0x6; // TCCR1B.CS <- 6
cpu.cycles = 511;
timer.tick();
expect(cpu.data[0xb2]).toEqual(1); // TCNT2 should be 2
cpu.cycles = 512;
timer.tick();
expect(cpu.data[0xb2]).toEqual(2); // TCNT2 should be 2
});
describe('16 bit timers', () => {
it('should increment 16-bit TCNT by 1', () => {
const timer = new AVRTimer(cpu, timer1Config);
cpu.writeData(0x85, 0x22); // TCNT1 <- 0x2233
cpu.writeData(0x84, 0x33); // ...
timer.tick();
expect(timer.TCNT).toEqual(0x2233);
cpu.writeData(0x80, 0x0); // WGM1 <- 0 (Normal)
cpu.writeData(0x81, 0x1); // TCCR1B.CS <- 1
cpu.cycles = 1;
timer.tick();
expect(cpu.dataView.getUint16(0x84, true)).toEqual(0x2234); // TCNT1 should increment
});
it('should set OCF0A flag when timer equals OCRA (16 bit mode)', () => {
const timer = new AVRTimer(cpu, timer1Config);
cpu.writeData(0x84, 0xee); // TCNT1 <- 0x10ee
cpu.writeData(0x85, 0x10); // ...
timer.tick();
cpu.writeData(0x88, 0xef); // OCR1A <- 0x10ef
cpu.writeData(0x89, 0x10); // ...
cpu.writeData(0x80, 0x0); // TCCR1A <- 0 (Normal Mode)
cpu.writeData(0x81, 0x1); // TCCR1B <- CS10
cpu.cycles = 1;
timer.tick();
expect(cpu.data[0x36]).toEqual(2); // TIFR1 should have OCF1A bit on
expect(cpu.pc).toEqual(0);
expect(cpu.cycles).toEqual(1);
});
it('should generate an overflow interrupt if timer overflows and interrupts enabled', () => {
const timer = new AVRTimer(cpu, timer1Config);
cpu.writeData(0x85, 0x3); // TCNT1 <- 0x3ff
cpu.writeData(0x84, 0xff); // ...
timer.tick();
cpu.writeData(0x80, 0x3); // TCCR1A <- WGM10 | WGM11 (Fast PWM, 10-bit)
cpu.writeData(0x81, 0x9); // TCCR1B <- WGM12 | CS10
console.log(timer.CS);
cpu.data[0x6f] = 0x1; // TIMSK1: TOIE1
cpu.data[95] = 0x80; // SREG: I-------
cpu.cycles = 1;
timer.tick();
expect(cpu.dataView.getUint16(0x84, true)).toEqual(0); // TCNT should be 0
expect(cpu.data[0x36]).toEqual(0); // TOV bit in TIFR should be clear
expect(cpu.pc).toEqual(0x1a);
expect(cpu.cycles).toEqual(3);
});
it('should reset the timer once it reaches ICR value in mode 12', () => {
const timer = new AVRTimer(cpu, timer1Config);
cpu.writeData(0x85, 0x50); // TCNT1 <- 0x500f
cpu.writeData(0x84, 0x0f); // ...
timer.tick();
cpu.writeData(0x87, 0x50); // ICR1 <- 0x5010
cpu.writeData(0x86, 0x10); // ...
cpu.writeData(0x81, 0x19); // TCCR1B <- WGM13 | WGM12 | CS10
cpu.cycles = 2; // 2 cycles should increment timer twice, beyond ICR1
timer.tick();
expect(cpu.dataView.getUint16(0x84, true)).toEqual(0); // TCNT should be 0
expect(cpu.data[0x36]).toEqual(0); // TOV bit in TIFR should be clear
expect(cpu.cycles).toEqual(2);
});
});
});
|
