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| author | Apexo | 2026-04-02 20:53:36 +0200 |
|---|---|---|
| committer | Apexo | 2026-04-02 20:53:36 +0200 |
| commit | 8926144705a8899a38e320696e7a03c256b406be (patch) | |
| tree | a58fb0839671b60f65673c62bbf33d88c6eb9d20 /src/peripherals/avrdx-adc.ts | |
| parent | improve main loop (diff) | |
| download | anduril-sim-8926144705a8899a38e320696e7a03c256b406be.tar.gz anduril-sim-8926144705a8899a38e320696e7a03c256b406be.tar.bz2 anduril-sim-8926144705a8899a38e320696e7a03c256b406be.zip | |
ADC: stop conversion when disabled via CTRLA
Diffstat (limited to 'src/peripherals/avrdx-adc.ts')
| -rw-r--r-- | src/peripherals/avrdx-adc.ts | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/src/peripherals/avrdx-adc.ts b/src/peripherals/avrdx-adc.ts index dc95d86..ed49ce6 100644 --- a/src/peripherals/avrdx-adc.ts +++ b/src/peripherals/avrdx-adc.ts @@ -81,6 +81,12 @@ export class AVRDxADC { enableMask: ADC_RESRDY_bm, } as const; + cpu.writeHooks[base + CTRLA] = (value) => { + cpu.data[base + CTRLA] = value; + if (!(value & ADC_ENABLE_bm)) this.stop(); + return true; + }; + // COMMAND register - writing STCONV starts a conversion cpu.writeHooks[base + COMMAND] = (value) => { cpu.data[base + COMMAND] = value; @@ -113,6 +119,13 @@ export class AVRDxADC { cpu.writeHooks[base + RESH] = () => true; } + private stop() { + if (this.conversionCallback) { + this.cpu.clearClockEvent(this.conversionCallback); + this.conversionCallback = null; + } + } + /** Set the voltage at the ADC pin (volts, after external divider). * The ADC result is computed at conversion time from this voltage, * the current VREF selection, and the accumulation count. */ @@ -140,9 +153,7 @@ export class AVRDxADC { const cpuCycles = adcCycles * prescDiv; // Schedule completion - if (this.conversionCallback) { - this.cpu.clearClockEvent(this.conversionCallback); - } + this.stop(); // TODO: do ADC CPU cycles depend on clock scaling? this.conversionCallback = this.cpu.addClockEvent(() => this.completeConversion(), cpuCycles); } |
