diff options
| author | Apexo | 2026-03-29 11:29:01 +0200 |
|---|---|---|
| committer | Apexo | 2026-03-29 11:29:01 +0200 |
| commit | 158116ad19455135b59929f4cdb569e55947ebbb (patch) | |
| tree | 7517d591d352a19069146b23633c691950fc5286 /src | |
| parent | avr8js submodule (diff) | |
| download | anduril-sim-158116ad19455135b59929f4cdb569e55947ebbb.tar.gz anduril-sim-158116ad19455135b59929f4cdb569e55947ebbb.tar.bz2 anduril-sim-158116ad19455135b59929f4cdb569e55947ebbb.zip | |
cleanup exports
Diffstat (limited to 'src')
| -rw-r--r-- | src/lights/d3aa.ts | 20 | ||||
| -rw-r--r-- | src/peripherals/avrdx-rstctrl.ts | 6 | ||||
| -rw-r--r-- | src/peripherals/avrdx-rtc-pit.ts | 2 |
3 files changed, 14 insertions, 14 deletions
diff --git a/src/lights/d3aa.ts b/src/lights/d3aa.ts index 40a390b..7586222 100644 --- a/src/lights/d3aa.ts +++ b/src/lights/d3aa.ts @@ -26,7 +26,7 @@ import { AVRDxWDT } from '../peripherals/avrdx-wdt'; // On AVR-Dx, data addresses 0x0000-0x001F are VPORTs (R0-R31 aren't memory-mapped). // This offset is added to all hardware data addresses so peripheral hooks // and data storage don't collide with the register file. -export const DATA_MEMORY_OFFSET = 32; +const DATA_MEMORY_OFFSET = 32; /* * memory layout @@ -42,19 +42,19 @@ export const DATA_MEMORY_OFFSET = 32; * are only hooked into memory for certain CPUs */ -export const EEPROM_START = 0x1400 + DATA_MEMORY_OFFSET; -export const EEPROM_SIZE = 256; +// const EEPROM_START = 0x1400 + DATA_MEMORY_OFFSET; +// const EEPROM_SIZE = 256; -export const SRAM_START = 0x7000 + DATA_MEMORY_OFFSET; -export const SRAM_SIZE = 0x1000; // 4 KB +const SRAM_START = 0x7000 + DATA_MEMORY_OFFSET; +const SRAM_SIZE = 0x1000; // 4 KB -export const MAPPED_PROGMEM_START = 0x8000 + DATA_MEMORY_OFFSET; -export const FLASH_SIZE = 0x8000; // 32 KB -export const FLASH_WORDS = FLASH_SIZE / 2; +const MAPPED_PROGMEM_START = 0x8000 + DATA_MEMORY_OFFSET; +const FLASH_SIZE = 0x8000; // 32 KB +const FLASH_WORDS = FLASH_SIZE / 2; -export const CPU_DATA_SIZE = 0x10000 + DATA_MEMORY_OFFSET; +const CPU_DATA_SIZE = 0x10000 + DATA_MEMORY_OFFSET; -export const CPU_FREQ = 12_000_000; // 12 MHz default clock +const CPU_FREQ = 12_000_000; // 12 MHz default clock // PORTA pins const SWITCH_PIN = 4; // PA4 - e-switch diff --git a/src/peripherals/avrdx-rstctrl.ts b/src/peripherals/avrdx-rstctrl.ts index 370b9c3..ce02552 100644 --- a/src/peripherals/avrdx-rstctrl.ts +++ b/src/peripherals/avrdx-rstctrl.ts @@ -4,9 +4,9 @@ import { type CPU } from 'avr8js/cpu/cpu'; import { type AVRDxCCP } from './avrdx-ccp'; -export const RSTFR = 0; -export const SWRR = 1; -export const SWRST_bm = 0x01; +const RSTFR = 0; +const SWRR = 1; +const SWRST_bm = 0x01; export class AVRDxRSTCTRL { /** Set this callback to handle software resets */ diff --git a/src/peripherals/avrdx-rtc-pit.ts b/src/peripherals/avrdx-rtc-pit.ts index 101f265..15feed0 100644 --- a/src/peripherals/avrdx-rtc-pit.ts +++ b/src/peripherals/avrdx-rtc-pit.ts @@ -16,7 +16,7 @@ const PERIOD_gm = 0x78; // bits [6:3] // PIT period to number of 32768Hz clock cycles // PERIOD field is bits [6:3] of CTRLA -export const PERIOD_CYCLES = [ +const PERIOD_CYCLES = [ 0, // 0x00: OFF 4, // 0x01: CYC4 8, // 0x02: CYC8 |