converted emisar-d18 to new API

(it's mostly the same as FW3A)

4 files changed, 133 insertions, 66 deletions

diff --git a/hwdef-Emisar_D18.h b/hwdef-Emisar_D18.h
deleted file mode 100644
index b9f5b2e..0000000
--- a/hwdef-Emisar_D18.h
+++ /dev/null
@@ -1,49 +0,0 @@
-// Emisar D18 (FET+13+1) driver layout
-// Copyright (C) 2019-2023 Selene ToyKeeper
-// SPDX-License-Identifier: GPL-3.0-or-later
-#pragma once
-
-/*
- *           ----
- *   Reset -|1  8|- VCC
- * eswitch -|2  7|- aux LED?
- *     FET -|3  6|- 13x7135
- *     GND -|4  5|-  1x7135
- *           ----
- */
-
-#define PWM_CHANNELS 3
-
-#ifndef SWITCH_PIN
-#define SWITCH_PIN   PB3    // pin 2
-#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt
-#endif
-
-#ifndef PWM1_PIN
-#define PWM1_PIN PB0        // pin 5, 1x7135 PWM
-#define PWM1_LVL OCR0A      // OCR0A is the output compare register for PB0
-#endif
-#ifndef PWM2_PIN
-#define PWM2_PIN PB1        // pin 6, 7x7135 PWM
-#define PWM2_LVL OCR0B      // OCR0B is the output compare register for PB1
-#endif
-#ifndef PWM3_PIN
-#define PWM3_PIN PB4        // pin 3, FET PWM
-#define PWM3_LVL OCR1B      // OCR1B is the output compare register for PB4
-#endif
-
-#ifndef AUXLED_PIN
-#define AUXLED_PIN PB2      // pin 7
-#endif
-#define ADC_PRSCL   0x07    // clk/128
-
-// average drop across diode on this hardware
-#ifndef VOLTAGE_FUDGE_FACTOR
-#define VOLTAGE_FUDGE_FACTOR 5  // add 0.25V
-#endif
-
-#define FAST 0xA3           // fast PWM both channels
-#define PHASE 0xA1          // phase-correct PWM both channels
-
-#define LAYOUT_DEFINED
-
diff --git a/hwdef-emisar-d18.h b/hwdef-emisar-d18.h
new file mode 100644
index 0000000..df08221
--- /dev/null
+++ b/hwdef-emisar-d18.h
@@ -0,0 +1,101 @@
+// Emisar D18 (FET+13+1) driver layout
+// Copyright (C) 2019-2023 Selene ToyKeeper
+// SPDX-License-Identifier: GPL-3.0-or-later
+#pragma once
+
+/*
+ *           ----
+ *   Reset -|1  8|- VCC
+ * eswitch -|2  7|- aux LED?
+ *     FET -|3  6|- 13x7135
+ *     GND -|4  5|-  1x7135
+ *           ----
+ */
+
+#define ATTINY 85
+#include <avr/io.h>
+
+#define HWDEF_C_FILE hwdef-fw3a.c
+
+// channel modes
+// * 0. FET+N+1 stacked
+#define NUM_CHANNEL_MODES   1
+enum CHANNEL_MODES {
+    CM_MAIN = 0,
+};
+
+#define DEFAULT_CHANNEL_MODE  CM_MAIN
+
+// right-most bit first, modes are in fedcba9876543210 order
+#define CHANNEL_MODES_ENABLED 0b00000001
+
+
+#define PWM_CHANNELS 3  // old, remove this
+
+#define PWM_BITS      8       // attiny85 only supports up to 8 bits
+#define PWM_GET       PWM_GET8
+#define PWM_DATATYPE  uint8_t
+#define PWM_DATATYPE2 uint16_t
+#define PWM1_DATATYPE uint8_t   // 1x7135 ramp
+#define PWM2_DATATYPE uint8_t   // 7x7135 ramp
+#define PWM3_DATATYPE uint8_t   // DD FET ramp
+
+#define PWM_TOP_INIT  255    // highest value used in top half of ramp
+
+// 1x7135 channel
+#define CH1_PIN  PB0        // pin 5, 1x7135 PWM
+#define CH1_PWM  OCR0A      // OCR0A is the output compare register for PB0
+
+// 7x7135 channel
+#define CH2_PIN  PB1        // pin 6, 7x7135 PWM
+#define CH2_PWM  OCR0B      // OCR0B is the output compare register for PB1
+
+// DD FET channel
+#define CH3_PIN  PB4        // pin 3, FET PWM
+#define CH3_PWM  OCR1B      // OCR1B is the output compare register for PB4
+
+// e-switch
+#ifndef SWITCH_PIN
+#define SWITCH_PIN   PB3    // pin 2
+#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt
+#endif
+
+#ifndef AUXLED_PIN
+#define AUXLED_PIN PB2      // pin 7
+#endif
+#define ADC_PRSCL   0x07    // clk/128
+
+// average drop across diode on this hardware
+#ifndef VOLTAGE_FUDGE_FACTOR
+#define VOLTAGE_FUDGE_FACTOR 5  // add 0.25V
+#endif
+
+#define FAST 0xA3           // fast PWM both channels
+#define PHASE 0xA1          // phase-correct PWM both channels
+
+
+inline void hwdef_setup() {
+
+    // configure PWM channels
+    DDRB = (1 << CH1_PIN)
+         | (1 << CH2_PIN)
+         | (1 << CH3_PIN);
+
+    // configure PWM channels
+    TCCR0B = 0x01; // pre-scaler for timer (1 => 1, 2 => 8, 3 => 64...)
+    TCCR0A = PHASE;
+
+    // Second PWM counter is ... weird
+    TCCR1 = _BV (CS10);
+    GTCCR = _BV (COM1B1) | _BV (PWM1B);
+    OCR1C = PWM_TOP_INIT;  // Set ceiling value to maximum
+
+    // configure e-switch
+    PORTB = (1 << SWITCH_PIN);  // e-switch is the only input
+    PCMSK = (1 << SWITCH_PIN);  // pin change interrupt uses this pin
+
+}
+
+
+#define LAYOUT_DEFINED
+
diff --git a/spaghetti-monster/anduril/cfg-emisar-d18.h b/spaghetti-monster/anduril/cfg-emisar-d18.h
index d59199c..3e5d3ae 100644
--- a/spaghetti-monster/anduril/cfg-emisar-d18.h
+++ b/spaghetti-monster/anduril/cfg-emisar-d18.h
@@ -4,25 +4,28 @@
 #pragma once
 
 #define MODEL_NUMBER "0141"
-#include "hwdef-Emisar_D18.h"
+#include "hwdef-emisar-d18.h"
 #include "hank-cfg.h"
 
+#define RAMP_SIZE 150
+
 // level_calc.py seventh 3 150 7135 1 1.4 117.99 7135 6 1 1706.86 FET 3 10 13000
 // (designed to make 1x hit at level 50, and Nx hit at level 100)
-#define RAMP_LENGTH 150
 #define PWM1_LEVELS 1,1,2,2,3,4,4,5,6,7,8,9,10,11,15,16,18,20,22,24,26,28,30,33,36,39,43,47,51,56,61,66,72,78,85,92,99,107,116,125,135,145,156,168,180,194,208,222,238,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0
 #define PWM2_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,7,8,10,11,13,14,16,18,19,21,23,26,28,30,33,35,38,41,44,47,51,54,58,62,66,70,75,79,84,90,95,101,106,112,119,126,133,140,147,155,164,172,181,190,200,210,221,232,243,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0
 #define PWM3_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,7,9,11,13,15,18,20,23,25,28,31,34,37,40,44,47,51,54,58,62,66,70,75,79,84,89,94,99,104,110,115,121,127,134,140,147,154,161,168,176,183,191,200,208,217,226,235,245,255
-#define MAX_1x7135 50
-#define MAX_Nx7135 100
-#define HALFSPEED_LEVEL 15
-#define QUARTERSPEED_LEVEL 6
+
+#define DEFAULT_LEVEL       50
+#define MAX_1x7135          50
+#define MAX_Nx7135          100
+#define HALFSPEED_LEVEL     15
+#define QUARTERSPEED_LEVEL  6
 
 // start at ~2000 lm after battery change, not ~150 lm (at Emisar's request)
 //#define DEFAULT_LEVEL MAX_Nx7135
 
 // go up to ~4000 lm
-#define RAMP_SMOOTH_FLOOR  1
+#define RAMP_SMOOTH_FLOOR 1
 #define RAMP_SMOOTH_CEIL  117
 // 20 36 52 68 84 [100] 117
 #define RAMP_DISCRETE_FLOOR 20
@@ -30,17 +33,29 @@
 #define RAMP_DISCRETE_STEPS 7
 
 // safe limit ~20% power / max regulated
-#define SIMPLE_UI_FLOOR 20
-#define SIMPLE_UI_CEIL MAX_Nx7135
-#define SIMPLE_UI_STEPS 5
+// 20 40 60 80 100
+#define SIMPLE_UI_FLOOR  20
+#define SIMPLE_UI_CEIL   MAX_Nx7135
+#define SIMPLE_UI_STEPS  5
 
 // only blink at max regulated level and ceiling
-#define BLINK_AT_RAMP_MIDDLE
-#define BLINK_AT_RAMP_MIDDLE_1 MAX_Nx7135
+//#define BLINK_AT_RAMP_MIDDLE
+//#define BLINK_AT_RAMP_MIDDLE_1 MAX_Nx7135
 #define BLINK_AT_RAMP_CEIL
+#ifdef BLINK_AT_RAMP_MIDDLE
+#undef BLINK_AT_RAMP_MIDDLE
+#endif
 
 // stop panicking at about ~40% power or ~5000 lm
 #define THERM_FASTER_LEVEL 125
 
+// enable extra features
+#define USE_SMOOTH_STEPS
+
+// for compatibility with other models
+#define USE_SOFT_FACTORY_RESET
+
 // too big, turn off extra features
 #undef USE_TACTICAL_MODE
+#undef USE_SOS_MODE
+
diff --git a/spaghetti-monster/anduril/cfg-fw3a.h b/spaghetti-monster/anduril/cfg-fw3a.h
index 7a8f417..1802f9b 100644
--- a/spaghetti-monster/anduril/cfg-fw3a.h
+++ b/spaghetti-monster/anduril/cfg-fw3a.h
@@ -15,11 +15,11 @@
 #define PWM2_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,4,6,8,10,13,15,17,19,22,24,26,29,31,34,37,39,42,45,48,51,54,57,60,64,67,70,74,77,81,85,88,92,96,100,104,108,112,116,121,125,130,134,139,143,148,153,158,163,168,173,179,184,189,195,201,206,212,218,224,230,236,243,249,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0
 #define PWM3_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8,19,31,43,55,67,79,91,104,117,130,143,157,170,184,198,212,226,240,255
 
-#define DEFAULT_LEVEL 50
-#define MAX_1x7135 65
-#define MAX_Nx7135 130
-#define HALFSPEED_LEVEL 15
-#define QUARTERSPEED_LEVEL 6
+#define DEFAULT_LEVEL       50
+#define MAX_1x7135          65
+#define MAX_Nx7135          130
+#define HALFSPEED_LEVEL     15
+#define QUARTERSPEED_LEVEL  6
 
 #define RAMP_SMOOTH_FLOOR 1
 #define RAMP_SMOOTH_CEIL  MAX_Nx7135