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| author | Selene ToyKeeper | 2020-07-06 14:24:28 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2020-07-06 14:24:28 -0600 |
| commit | 24270b394a0119bff8681ed75c1e21876c11439f (patch) | |
| tree | 432756e4b5bf26bac78c7809128d52e0d531262c /hwdef-BLF_GT.h | |
| parent | added a compile flag to fix compatibility with GCC 7/8/9's new semantics for ... (diff) | |
| parent | merged in support for Noctigon K1-SBT90.2 (diff) | |
| download | anduril-24270b394a0119bff8681ed75c1e21876c11439f.tar.gz anduril-24270b394a0119bff8681ed75c1e21876c11439f.tar.bz2 anduril-24270b394a0119bff8681ed75c1e21876c11439f.zip | |
merged nearly a year of updates from the fsm branch, including the new product map
Diffstat (limited to 'hwdef-BLF_GT.h')
| -rw-r--r-- | hwdef-BLF_GT.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/hwdef-BLF_GT.h b/hwdef-BLF_GT.h index 01dbdbd..51b391d 100644 --- a/hwdef-BLF_GT.h +++ b/hwdef-BLF_GT.h @@ -34,24 +34,24 @@ #ifndef VOLTAGE_PIN #define VOLTAGE_PIN PB2 // pin 7, voltage ADC #define VOLTAGE_CHANNEL 0x01 // MUX 01 corresponds with PB2 -#define VOLTAGE_ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 +#define VOLTAGE_ADC ADC1D // Digital input disable bit corresponding with PB2 +// inherited from tk-attiny.h +//#define VOLTAGE_ADC_DIDR DIDR0 // DIDR for ADC1 // 1.1V reference, left-adjust, ADC1/PB2 //#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | (1 << ADLAR) | VOLTAGE_CHANNEL) // 1.1V reference, no left-adjust, ADC1/PB2 #define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL) #endif -#define ADC_PRSCL 0x06 // clk/64 +#define ADC_PRSCL 0x07 // clk/128 // Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line) #ifndef ADC_44 -#define ADC_44 184 +#define ADC_44 (184*4) #endif #ifndef ADC_22 -#define ADC_22 92 +#define ADC_22 (92*4) #endif -#define TEMP_CHANNEL 0b00001111 - #define FAST 0xA3 // fast PWM both channels #define PHASE 0xA1 // phase-correct PWM both channels |