aboutsummaryrefslogtreecommitdiff
path: root/hwdef-BLF_Q8-T1616.h
diff options
context:
space:
mode:
authorSelene ToyKeeper2022-04-09 02:46:15 -0600
committerSelene ToyKeeper2022-04-09 02:46:15 -0600
commit3a0f2bb9fa050bf9a0e8dd38cf32d316e1b18f56 (patch)
tree0bfc60c84622b2b23593a76e6dae2d94ad8078be /hwdef-BLF_Q8-T1616.h
parentk9.3 tint-toggle build is broken, generate a better fail error (until it's fi... (diff)
parentmerged anduril2 branch for upstream changes (diff)
downloadanduril-3a0f2bb9fa050bf9a0e8dd38cf32d316e1b18f56.tar.gz
anduril-3a0f2bb9fa050bf9a0e8dd38cf32d316e1b18f56.tar.bz2
anduril-3a0f2bb9fa050bf9a0e8dd38cf32d316e1b18f56.zip
merged sofirn sp10-pro branch (should have done it months ago, but forgot)
Diffstat (limited to 'hwdef-BLF_Q8-T1616.h')
-rw-r--r--hwdef-BLF_Q8-T1616.h14
1 files changed, 10 insertions, 4 deletions
diff --git a/hwdef-BLF_Q8-T1616.h b/hwdef-BLF_Q8-T1616.h
index 2a0e6ff..d6ad760 100644
--- a/hwdef-BLF_Q8-T1616.h
+++ b/hwdef-BLF_Q8-T1616.h
@@ -61,8 +61,8 @@ Driver pinout:
// ... so just hardcode it in each hwdef file instead
inline void hwdef_setup() {
- // set up the system clock to run at 5 MHz instead of the default 3.33 MHz
- _PROTECTED_WRITE( CLKCTRL.MCLKCTRLB, CLKCTRL_PDIV_4X_gc | CLKCTRL_PEN_bm );
+ // set up the system clock to run at 10 MHz instead of the default 3.33 MHz
+ _PROTECTED_WRITE( CLKCTRL.MCLKCTRLB, CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm );
//VPORTA.DIR = ...;
VPORTB.DIR = PIN0_bm | PIN1_bm | PIN5_bm; // Outputs: Aux LED and PWMs
@@ -91,8 +91,14 @@ inline void hwdef_setup() {
PORTC.PIN3CTRL = PORT_PULLUPEN_bm;
// set up the PWM
- // TODO: add references to MCU documentation
- TCA0.SINGLE.CTRLB = TCA_SINGLE_CMP0EN_bm | TCA_SINGLE_CMP1EN_bm | TCA_SINGLE_WGMODE_SINGLESLOPE_gc;
+ // https://ww1.microchip.com/downloads/en/DeviceDoc/ATtiny1614-16-17-DataSheet-DS40002204A.pdf
+ // PB0 is TCA0:WO0, use TCA_SINGLE_CMP0EN_bm
+ // PB1 is TCA0:WO1, use TCA_SINGLE_CMP1EN_bm
+ // PB2 is TCA0:WO2, use TCA_SINGLE_CMP2EN_bm
+ // For Fast (Single Slope) PWM use TCA_SINGLE_WGMODE_SINGLESLOPE_gc
+ // For Phase Correct (Dual Slope) PWM use TCA_SINGLE_WGMODE_DSBOTTOM_gc
+ // See the manual for other pins, clocks, configs, portmux, etc
+ TCA0.SINGLE.CTRLB = TCA_SINGLE_CMP0EN_bm | TCA_SINGLE_CMP1EN_bm | TCA_SINGLE_WGMODE_DSBOTTOM_gc;
TCA0.SINGLE.PER = 255;
TCA0.SINGLE.CTRLA = TCA_SINGLE_CLKSEL_DIV1_gc | TCA_SINGLE_ENABLE_bm;
}