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| author | Selene ToyKeeper | 2020-07-06 14:24:28 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2020-07-06 14:24:28 -0600 |
| commit | 24270b394a0119bff8681ed75c1e21876c11439f (patch) | |
| tree | 432756e4b5bf26bac78c7809128d52e0d531262c /hwdef-FW3A.h | |
| parent | added a compile flag to fix compatibility with GCC 7/8/9's new semantics for ... (diff) | |
| parent | merged in support for Noctigon K1-SBT90.2 (diff) | |
| download | anduril-24270b394a0119bff8681ed75c1e21876c11439f.tar.gz anduril-24270b394a0119bff8681ed75c1e21876c11439f.tar.bz2 anduril-24270b394a0119bff8681ed75c1e21876c11439f.zip | |
merged nearly a year of updates from the fsm branch, including the new product map
Diffstat (limited to 'hwdef-FW3A.h')
| -rw-r--r-- | hwdef-FW3A.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/hwdef-FW3A.h b/hwdef-FW3A.h index 0b94635..e8875d7 100644 --- a/hwdef-FW3A.h +++ b/hwdef-FW3A.h @@ -35,16 +35,13 @@ //#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2 //#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 #endif -#define ADC_PRSCL 0x06 // clk/64 +#define ADC_PRSCL 0x07 // clk/128 // average drop across diode on this hardware #ifndef VOLTAGE_FUDGE_FACTOR #define VOLTAGE_FUDGE_FACTOR 5 // add 0.25V #endif -//#define TEMP_DIDR ADC4D -#define TEMP_CHANNEL 0b00001111 - #define FAST 0xA3 // fast PWM both channels #define PHASE 0xA1 // phase-correct PWM both channels |