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| author | Selene ToyKeeper | 2019-08-11 15:16:23 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2019-08-11 15:16:23 -0600 |
| commit | 89a86871aa6330218043586f0347c0c1e7c79dab (patch) | |
| tree | e3a4cc2a4517e5563e91cdaaf86718170d4f0a37 /hwdef-Mateminco_MF01S.h | |
| parent | Added setup info for Fedora. (diff) | |
| parent | added scripts to flash attiny1634, which were missing before (diff) | |
| download | anduril-89a86871aa6330218043586f0347c0c1e7c79dab.tar.gz anduril-89a86871aa6330218043586f0347c0c1e7c79dab.tar.bz2 anduril-89a86871aa6330218043586f0347c0c1e7c79dab.zip | |
merged fsm to trunk... lots of updates:
+ attiny1634 support
+ Emisar D4v2 support
+ Mateminco MF01S / MT18 support
+ Fireflies E01 and E07v2 support
+ RGB aux LED support
+ added factory reset function
+ added manual / automatic memory toggle
+ added 2-level brightness during lockout
+ added Fireflies UI
+ made momentary mode also support strobe-group modes
* thermal regulation rewritten, behaves mostly better now
* strobe modes auto-reverse their ramp now
* muggle mode fixes
* UI diagram and manual updated
* button timing adjusted, and compile-time options added for it
* general refactoring
Diffstat (limited to 'hwdef-Mateminco_MF01S.h')
| -rw-r--r-- | hwdef-Mateminco_MF01S.h | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/hwdef-Mateminco_MF01S.h b/hwdef-Mateminco_MF01S.h new file mode 100644 index 0000000..ab1c5bf --- /dev/null +++ b/hwdef-Mateminco_MF01S.h @@ -0,0 +1,60 @@ +#ifndef HWDEF_MF01S_H +#define HWDEF_MF01S_H + +/* MF01S driver layout + * ---- + * Reset -|1 8|- VCC (unused) + * eswitch -|2 7|- Voltage divider (2S) + * AUX LED -|3 6|- PWM (FET) + * GND -|4 5|- PWM (smaller FET) + * ---- + */ + +#define PWM_CHANNELS 2 + +#ifndef AUXLED_PIN +#define AUXLED_PIN PB4 // pin 3 +#endif + +#ifndef SWITCH_PIN +#define SWITCH_PIN PB3 // pin 2 +#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt +#endif + +#ifndef PWM1_PIN +#define PWM1_PIN PB0 // pin 5, 1x7135 PWM +#define PWM1_LVL OCR0A // OCR0A is the output compare register for PB0 +#endif +#ifndef PWM2_PIN +#define PWM2_PIN PB1 // pin 6, FET PWM +#define PWM2_LVL OCR0B // OCR0B is the output compare register for PB1 +#endif + +#define USE_VOLTAGE_DIVIDER // use a voltage divider on pin 7, not VCC +#ifndef VOLTAGE_PIN +#define VOLTAGE_PIN PB2 // pin 7, voltage ADC +#define VOLTAGE_CHANNEL 0x01 // MUX 01 corresponds with PB2 +#define VOLTAGE_ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 +// 1.1V reference, left-adjust, ADC1/PB2 +//#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | (1 << ADLAR) | VOLTAGE_CHANNEL) +// 1.1V reference, no left-adjust, ADC1/PB2 +#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL) +#endif +#define ADC_PRSCL 0x06 // clk/64 + +// Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line) +#ifndef ADC_44 +#define ADC_44 234 +#endif +#ifndef ADC_22 +#define ADC_22 117 +#endif + +#define TEMP_CHANNEL 0b00001111 + +#define FAST 0xA3 // fast PWM both channels +#define PHASE 0xA1 // phase-correct PWM both channels + +#define LAYOUT_DEFINED + +#endif |