diff options
| author | Selene ToyKeeper | 2023-10-29 13:05:38 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2023-10-29 13:05:38 -0600 |
| commit | bcaf2686d9f0570dfbc508ddcac95ee55d501f48 (patch) | |
| tree | 801ccd6ec9d94d0144e1a200fb5bd610cdcd4e7e /hwdef-noctigon-dm11-boost.c | |
| parent | fixed blf-lt1-t1616, after testing on actual hardware (diff) | |
| download | anduril-bcaf2686d9f0570dfbc508ddcac95ee55d501f48.tar.gz anduril-bcaf2686d9f0570dfbc508ddcac95ee55d501f48.tar.bz2 anduril-bcaf2686d9f0570dfbc508ddcac95ee55d501f48.zip | |
converted noctigon-dm11-boost to use PWM+DSM, and recalibrated timing for delays + smooth steps
Anduril has gradually gotten faster over the years, apparently, so it
needed longer delays to get accurate-ish timing for beacon and other modes.
Adding DSM also changes the timing perceptibly, so I made it possible to
calibrate the delay fudge factor on a per-build basis.
Diffstat (limited to 'hwdef-noctigon-dm11-boost.c')
| -rw-r--r-- | hwdef-noctigon-dm11-boost.c | 63 |
1 files changed, 50 insertions, 13 deletions
diff --git a/hwdef-noctigon-dm11-boost.c b/hwdef-noctigon-dm11-boost.c index 08e2798..932323a 100644 --- a/hwdef-noctigon-dm11-boost.c +++ b/hwdef-noctigon-dm11-boost.c @@ -1,11 +1,11 @@ // Noctigon DM11 (boost driver) PWM helper functions // Copyright (C) 2023 Selene ToyKeeper // SPDX-License-Identifier: GPL-3.0-or-later - #pragma once #include "chan-rgbaux.c" + void set_level_zero(); void set_level_main(uint8_t level); @@ -22,6 +22,12 @@ Channel channels[] = { void set_level_zero() { + // disable timer overflow interrupt + // (helps improve button press handling from Off state) + DSM_INTCTRL &= ~DSM_OVF_bm; + + // turn off all LEDs + ch1_dsm_lvl = 0; CH1_PWM = 0; PWM_CNT = 0; // reset phase CH1_ENABLE_PORT &= ~(1 << CH1_ENABLE_PIN ); // disable opamp @@ -30,28 +36,59 @@ void set_level_zero() { // single set of LEDs with single power channel, boost void set_level_main(uint8_t level) { - CH1_ENABLE_PORT |= (1 << CH1_ENABLE_PIN ); // enable opamp - CH1_ENABLE_PORT2 |= (1 << CH1_ENABLE_PIN2); // enable PMIC + PWM_DATATYPE ch1 = PWM_GET(pwm1_levels, level); - PWM_DATATYPE ch1_pwm = PWM_GET(pwm1_levels, level); - // pulse frequency modulation, a.k.a. dynamic PWM - uint16_t top = PWM_GET16(pwm_tops, level); + // set delta-sigma soft levels + ch1_dsm_lvl = ch1; + + // set hardware PWM levels and init dsm loop + CH1_PWM = ch1_pwm = ch1 >> 7; + + // enable timer overflow interrupt so DSM can work + DSM_INTCTRL |= DSM_OVF_bm; - CH1_PWM = ch1_pwm; - // wait to sync the counter and avoid flashes - while(actual_level && (PWM_CNT > (top - 32))) {} - PWM_TOP = top; // force reset phase when turning on from zero // (because otherwise the initial response is inconsistent) if (! actual_level) PWM_CNT = 0; + + CH1_ENABLE_PORT |= (1 << CH1_ENABLE_PIN ); // enable opamp + CH1_ENABLE_PORT2 |= (1 << CH1_ENABLE_PIN2); // enable PMIC } +// delta-sigma modulation of PWM outputs +// happens on each Timer overflow (every 512 cpu clock cycles) +// uses 8-bit pwm w/ 7-bit dsm (0b 0PPP PPPP PDDD DDDD) +ISR(DSM_vect) { + // set new hardware values first, + // for best timing (reduce effect of interrupt jitter) + CH1_PWM = ch1_pwm; + + // calculate next values, now that timing matters less + + // accumulate error + ch1_dsm += (ch1_dsm_lvl & 0x007f); + // next PWM = base PWM value + carry bit + ch1_pwm = (ch1_dsm_lvl >> 7) + (ch1_dsm > 0x7f); + // clear carry bit + ch1_dsm &= 0x7f; +} + + bool gradual_tick_main(uint8_t gt) { - PWM_DATATYPE pwm1 = PWM_GET(pwm1_levels, gt); + PWM_DATATYPE ch1 = PWM_GET(pwm1_levels, gt); + + // adjust multiple times based on current brightness + // (so it adjusts faster/coarser when bright, slower/finer when dim) + + // higher shift = slower/finer adjustments + const uint8_t shift = 9; // ((255 << 7) >> 9) = 63 max + uint8_t steps; - GRADUAL_ADJUST_SIMPLE(pwm1, CH1_PWM); + steps = ch1_dsm_lvl >> shift; + for (uint8_t i=0; i<=steps; i++) + GRADUAL_ADJUST_SIMPLE(ch1, ch1_dsm_lvl); - if ( (pwm1 == CH1_PWM) + if ((ch1 == ch1_dsm_lvl) ) { return true; // done } |
