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| author | Selene ToyKeeper | 2023-10-29 13:05:38 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2023-10-29 13:05:38 -0600 |
| commit | bcaf2686d9f0570dfbc508ddcac95ee55d501f48 (patch) | |
| tree | 801ccd6ec9d94d0144e1a200fb5bd610cdcd4e7e /hwdef-noctigon-m44.h | |
| parent | fixed blf-lt1-t1616, after testing on actual hardware (diff) | |
| download | anduril-bcaf2686d9f0570dfbc508ddcac95ee55d501f48.tar.gz anduril-bcaf2686d9f0570dfbc508ddcac95ee55d501f48.tar.bz2 anduril-bcaf2686d9f0570dfbc508ddcac95ee55d501f48.zip | |
converted noctigon-dm11-boost to use PWM+DSM, and recalibrated timing for delays + smooth steps
Anduril has gradually gotten faster over the years, apparently, so it
needed longer delays to get accurate-ish timing for beacon and other modes.
Adding DSM also changes the timing perceptibly, so I made it possible to
calibrate the delay fudge factor on a per-build basis.
Diffstat (limited to 'hwdef-noctigon-m44.h')
| -rw-r--r-- | hwdef-noctigon-m44.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/hwdef-noctigon-m44.h b/hwdef-noctigon-m44.h index a41ea79..094e555 100644 --- a/hwdef-noctigon-m44.h +++ b/hwdef-noctigon-m44.h @@ -65,7 +65,7 @@ enum channel_modes_e { #define PWM_CHANNELS 1 // old, remove this -#define PWM_BITS 16 // 0 to 32640 (0 to 255 PWM + 0 to 127 DSM) at constant kHz +#define PWM_BITS 16 // 0 to 32640 (0 to 255 PWM + 0 to 127 DSM) at constant kHz #define PWM_GET PWM_GET16 #define PWM_DATATYPE uint16_t #define PWM_DATATYPE2 uint32_t // only needs 32-bit if ramp values go over 255 @@ -105,8 +105,8 @@ uint8_t ch2_pwm, ch2_dsm; // e-switch #define SWITCH_PIN PA7 // pin 20 #define SWITCH_PCINT PCINT7 // pin 20 pin change interrupt -#define SWITCH_PCIE PCIE0 // PCIE1 is for PCINT[7:0] -#define SWITCH_PCMSK PCMSK0 // PCMSK1 is for PCINT[7:0] +#define SWITCH_PCIE PCIE0 // PCIE0 is for PCINT[7:0] +#define SWITCH_PCMSK PCMSK0 // PCMSK0 is for PCINT[7:0] #define SWITCH_PORT PINA // PINA or PINB or PINC #define SWITCH_PUE PUEA // pullup group A #define PCINT_vect PCINT0_vect // ISR for PCINT[7:0] @@ -178,14 +178,14 @@ inline void hwdef_setup() { // CS1[2:0]: 0,0,1: clk/1 (No prescaling) (DS table 12-6) // COM1A[1:0]: 1,0: PWM OC1A in the normal direction (DS table 12-4) // COM1B[1:0]: 1,0: PWM OC1B in the normal direction (DS table 12-4) - TCCR1A = (1<<WGM11) | (0<<WGM10) // adjustable PWM (TOP=ICR1) (DS table 12-5) - | (1<<COM1A1) | (0<<COM1A0) // PWM 1A in normal direction (DS table 12-4) - | (1<<COM1B1) | (0<<COM1B0) // PWM 1B in normal direction (DS table 12-4) - ; - TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6) - //| (1<<WGM13) | (1<<WGM12) // fast adjustable PWM (DS table 12-5) - | (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) - ; + TCCR1A = (1<<WGM11) | (0<<WGM10) // adjustable PWM (TOP=ICR1) (DS table 12-5) + | (1<<COM1A1) | (0<<COM1A0) // PWM 1A in normal direction (DS table 12-4) + | (1<<COM1B1) | (0<<COM1B0) // PWM 1B in normal direction (DS table 12-4) + ; + TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6) + //| (1<<WGM13) | (1<<WGM12) // fast adjustable PWM (DS table 12-5) + | (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5) + ; // set PWM resolution PWM_TOP = PWM_TOP_INIT; |