aboutsummaryrefslogtreecommitdiff
path: root/hw/hank/emisar-d4v2
diff options
context:
space:
mode:
Diffstat (limited to 'hw/hank/emisar-d4v2')
-rw-r--r--hw/hank/emisar-d4v2/cfg.h64
-rw-r--r--hw/hank/emisar-d4v2/hwdef.c61
-rw-r--r--hw/hank/emisar-d4v2/hwdef.h171
3 files changed, 296 insertions, 0 deletions
diff --git a/hw/hank/emisar-d4v2/cfg.h b/hw/hank/emisar-d4v2/cfg.h
new file mode 100644
index 0000000..0f0bb17
--- /dev/null
+++ b/hw/hank/emisar-d4v2/cfg.h
@@ -0,0 +1,64 @@
+// Emisar D4v2 config options for Anduril
+// Copyright (C) 2018-2023 Selene ToyKeeper
+// SPDX-License-Identifier: GPL-3.0-or-later
+#pragma once
+
+#define MODEL_NUMBER "0113"
+#include "hwdef-emisar-d4v2.h"
+#include "hank-cfg.h"
+// ATTINY: 1634
+
+#define RAMP_SIZE 150
+
+// 7135 at 75/150
+// level_calc.py 5.7895 2 150 7135 1 0.1 130 FET 1 10 3000 --pwm dyn:74:4096:255:3
+// (with some manual tweaks)
+// non-zero part of FET channel calculated with:
+// level_calc.py 3 1 75 7135 2 500 3000
+#define PWM1_LEVELS 1,1,2,3,3,4,5,6,7,8,9,11,12,13,15,16,18,19,21,23,26,27,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,71,74,76,78,80,82,85,87,90,93,96,100,103,107,112,116,122,127,133,140,147,154,163,171,182,192,203,215,228,241,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0
+#define PWM2_LEVELS 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,4,5,7,9,11,13,15,17,19,21,23,25,27,29,32,34,36,39,41,43,46,49,51,54,57,59,62,65,68,71,74,77,80,83,86,90,93,96,100,103,107,110,114,117,121,125,129,133,137,141,145,149,153,157,162,166,170,175,179,184,189,193,198,203,208,213,218,223,228,233,239,244,249,255
+#define PWM_TOPS 4095,2701,3200,3586,2518,2778,2834,2795,2705,2587,2455,2582,2412,2247,2256,2091,2062,1907,1860,1802,1737,1605,1542,1477,1412,1347,1284,1222,1162,1105,1050,997,946,898,853,810,768,730,693,658,625,594,564,536,503,485,462,439,418,398,384,366,353,340,327,319,307,298,292,284,280,273,269,266,263,260,258,256,256,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255
+
+#define MAX_1x7135 75
+#define DEFAULT_LEVEL 50
+#define MIN_THERM_STEPDOWN 70 // should be above highest dyn_pwm level
+#define HALFSPEED_LEVEL 20
+#define QUARTERSPEED_LEVEL 5
+
+#define RAMP_SMOOTH_FLOOR 1
+#define RAMP_SMOOTH_CEIL 130
+// 20, 38, 56, [75], 93, 111, 130
+#define RAMP_DISCRETE_FLOOR 20
+#define RAMP_DISCRETE_CEIL RAMP_SMOOTH_CEIL
+#define RAMP_DISCRETE_STEPS 7
+
+// 20, 40, 60, 80, 100
+#define SIMPLE_UI_FLOOR 20
+#define SIMPLE_UI_CEIL 100
+#define SIMPLE_UI_STEPS 5
+
+// stop panicking at ~25% power or ~1000 lm
+#define THERM_FASTER_LEVEL 110
+
+#define THERM_CAL_OFFSET 5
+
+// show each channel while it scroll by in the menu
+#define USE_CONFIG_COLORS
+
+// blink numbers on the main LEDs by default (but allow user to change it)
+#define DEFAULT_BLINK_CHANNEL CM_MAIN
+
+// use aux red + aux blue for police strobe
+#define USE_POLICE_COLOR_STROBE_MODE
+#define POLICE_STROBE_USES_AUX
+#define POLICE_COLOR_STROBE_CH1 CM_AUXRED
+#define POLICE_COLOR_STROBE_CH2 CM_AUXBLU
+
+// the default of 26 looks a bit rough, so increase it to make it smoother
+#define CANDLE_AMPLITUDE 33
+
+// don't blink while ramping
+#ifdef BLINK_AT_RAMP_MIDDLE
+#undef BLINK_AT_RAMP_MIDDLE
+#endif
+
diff --git a/hw/hank/emisar-d4v2/hwdef.c b/hw/hank/emisar-d4v2/hwdef.c
new file mode 100644
index 0000000..026b30d
--- /dev/null
+++ b/hw/hank/emisar-d4v2/hwdef.c
@@ -0,0 +1,61 @@
+// Emisar D4v2 PWM helper functions
+// Copyright (C) 2017-2023 Selene ToyKeeper
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#pragma once
+
+#include "chan-rgbaux.c"
+
+void set_level_zero();
+
+void set_level_main(uint8_t level);
+bool gradual_tick_main(uint8_t gt);
+
+
+Channel channels[] = {
+ { // main LEDs
+ .set_level = set_level_main,
+ .gradual_tick = gradual_tick_main
+ },
+ RGB_AUX_CHANNELS
+};
+
+
+void set_level_zero() {
+ CH1_PWM = 0;
+ CH2_PWM = 0;
+ PWM_CNT = 0; // reset phase
+}
+
+// single set of LEDs with 2 stacked power channels, DDFET+1 or DDFET+linear
+void set_level_main(uint8_t level) {
+ PWM_DATATYPE ch1_pwm = PWM_GET(pwm1_levels, level);
+ PWM_DATATYPE ch2_pwm = PWM_GET(pwm2_levels, level);
+ // pulse frequency modulation, a.k.a. dynamic PWM
+ uint16_t top = PWM_GET16(pwm_tops, level);
+
+ CH1_PWM = ch1_pwm;
+ CH2_PWM = ch2_pwm;
+ // wait to sync the counter and avoid flashes
+ while(actual_level && (PWM_CNT > (top - 32))) {}
+ PWM_TOP = top;
+ // force reset phase when turning on from zero
+ // (because otherwise the initial response is inconsistent)
+ if (! actual_level) PWM_CNT = 0;
+}
+
+bool gradual_tick_main(uint8_t gt) {
+ PWM_DATATYPE pwm1 = PWM_GET(pwm1_levels, gt);
+ PWM_DATATYPE pwm2 = PWM_GET(pwm2_levels, gt);
+
+ GRADUAL_ADJUST_STACKED(pwm1, CH1_PWM, PWM_TOP_INIT);
+ GRADUAL_ADJUST_SIMPLE (pwm2, CH2_PWM);
+
+ if ( (pwm1 == CH1_PWM)
+ && (pwm2 == CH2_PWM)
+ ) {
+ return true; // done
+ }
+ return false; // not done yet
+}
+
diff --git a/hw/hank/emisar-d4v2/hwdef.h b/hw/hank/emisar-d4v2/hwdef.h
new file mode 100644
index 0000000..96c57a9
--- /dev/null
+++ b/hw/hank/emisar-d4v2/hwdef.h
@@ -0,0 +1,171 @@
+// hwdef for Emisar D4v2 (attiny1634)
+// Copyright (C) 2018-2023 Selene ToyKeeper
+// SPDX-License-Identifier: GPL-3.0-or-later
+#pragma once
+
+/*
+ * Pin / Name / Function
+ * 1 PA6 FET PWM (direct drive) (PWM1B)
+ * 2 PA5 R: red aux LED (PWM0B)
+ * 3 PA4 G: green aux LED
+ * 4 PA3 B: blue aux LED
+ * 5 PA2 e-switch
+ * 6 PA1 button LED
+ * 7 PA0 (none)
+ * 8 GND GND
+ * 9 VCC VCC
+ * 10 PC5 (none)
+ * 11 PC4 (none)
+ * 12 PC3 RESET
+ * 13 PC2 (none)
+ * 14 PC1 SCK
+ * 15 PC0 (none) PWM0A
+ * 16 PB3 7135 PWM (PWM1A)
+ * 17 PB2 MISO
+ * 18 PB1 MOSI
+ * 19 PB0 (none)
+ * 20 PA7 (none)
+ * ADC12 thermal sensor
+ */
+
+#define ATTINY 1634
+#include <avr/io.h>
+
+#ifndef HWDEF_C_FILE
+#define HWDEF_C_FILE hwdef-emisar-d4v2.c
+#endif
+
+// allow using aux LEDs as extra channel modes
+#include "chan-rgbaux.h"
+
+// channel modes:
+// * 0. FET+7135 stacked
+// * 1+. aux RGB
+#define NUM_CHANNEL_MODES (1 + NUM_RGB_AUX_CHANNEL_MODES)
+enum CHANNEL_MODES {
+ CM_MAIN = 0,
+ RGB_AUX_ENUMS
+};
+
+#define DEFAULT_CHANNEL_MODE CM_MAIN
+
+// right-most bit first, modes are in fedcba9876543210 order
+#define CHANNEL_MODES_ENABLED 0b0000000000000001
+// no args
+//#define USE_CHANNEL_MODE_ARGS
+//#define CHANNEL_MODE_ARGS 0,0,0,0,0,0,0,0
+
+
+#define PWM_CHANNELS 2 // old, remove this
+
+#define PWM_BITS 16 // dynamic 16-bit, but never goes over 255
+#define PWM_GET PWM_GET8
+#define PWM_DATATYPE uint16_t // is used for PWM_TOPS (which goes way over 255)
+#define PWM_DATATYPE2 uint16_t // only needs 32-bit if ramp values go over 255
+#define PWM1_DATATYPE uint8_t // 1x7135 ramp
+#define PWM2_DATATYPE uint8_t // DD FET ramp
+
+// PWM parameters of both channels are tied together because they share a counter
+#define PWM_TOP ICR1 // holds the TOP value for for variable-resolution PWM
+#define PWM_TOP_INIT 255 // highest value used in top half of ramp
+#define PWM_CNT TCNT1 // for dynamic PWM, reset phase
+
+// 1x7135 channel
+#define CH1_PIN PB3 // pin 16, 1x7135 PWM
+#define CH1_PWM OCR1A // OCR1A is the output compare register for PB3
+
+// DD FET channel
+#define CH2_PIN PA6 // pin 1, DD FET PWM
+#define CH2_PWM OCR1B // OCR1B is the output compare register for PA6
+
+// e-switch
+#define SWITCH_PIN PA2 // pin 5
+#define SWITCH_PCINT PCINT2 // pin 5 pin change interrupt
+#define SWITCH_PCIE PCIE0 // PCIE0 is for PCINT[7:0]
+#define SWITCH_PCMSK PCMSK0 // PCMSK0 is for PCINT[7:0]
+#define SWITCH_PORT PINA // PINA or PINB or PINC
+#define SWITCH_PUE PUEA // pullup group A
+#define PCINT_vect PCINT0_vect // ISR for PCINT[7:0]
+
+
+#define ADC_PRSCL 0x07 // clk/128
+
+// average drop across diode on this hardware
+#ifndef VOLTAGE_FUDGE_FACTOR
+#define VOLTAGE_FUDGE_FACTOR 4 // add 0.20V (measured 0.22V)
+#endif
+
+// this light has aux LEDs under the optic
+#define AUXLED_R_PIN PA5 // pin 2
+#define AUXLED_G_PIN PA4 // pin 3
+#define AUXLED_B_PIN PA3 // pin 4
+#define AUXLED_RGB_PORT PORTA // PORTA or PORTB or PORTC
+#define AUXLED_RGB_DDR DDRA // DDRA or DDRB or DDRC
+#define AUXLED_RGB_PUE PUEA // PUEA or PUEB or PUEC
+
+#define BUTTON_LED_PIN PA1 // pin 6
+#define BUTTON_LED_PORT PORTA // for all "PA" pins
+#define BUTTON_LED_DDR DDRA // for all "PA" pins
+#define BUTTON_LED_PUE PUEA // for all "PA" pins
+
+// this light has three aux LED channels: R, G, B
+#define USE_AUX_RGB_LEDS
+// it also has an independent LED in the button
+#define USE_BUTTON_LED
+// the aux LEDs are front-facing, so turn them off while main LEDs are on
+#ifdef USE_INDICATOR_LED_WHILE_RAMPING
+#undef USE_INDICATOR_LED_WHILE_RAMPING
+#endif
+
+
+inline void hwdef_setup() {
+ // enable output ports
+ // 7135
+ DDRB = (1 << CH1_PIN);
+ // DD FET, aux R/G/B, button LED
+ DDRA = (1 << CH2_PIN)
+ | (1 << AUXLED_R_PIN)
+ | (1 << AUXLED_G_PIN)
+ | (1 << AUXLED_B_PIN)
+ | (1 << BUTTON_LED_PIN)
+ ;
+
+ // configure PWM
+ // Setup PWM. F_pwm = F_clkio / 2 / N / TOP, where N = prescale factor, TOP = top of counter
+ // pre-scale for timer: N = 1
+ // WGM1[3:0]: 1,0,1,0: PWM, Phase Correct, adjustable (DS table 12-5)
+ // CS1[2:0]: 0,0,1: clk/1 (No prescaling) (DS table 12-6)
+ // COM1A[1:0]: 1,0: PWM OC1A in the normal direction (DS table 12-4)
+ // COM1B[1:0]: 1,0: PWM OC1B in the normal direction (DS table 12-4)
+ TCCR1A = (1<<WGM11) | (0<<WGM10) // adjustable PWM (TOP=ICR1) (DS table 12-5)
+ | (1<<COM1A1) | (0<<COM1A0) // PWM 1A in normal direction (DS table 12-4)
+ | (1<<COM1B1) | (0<<COM1B0) // PWM 1B in normal direction (DS table 12-4)
+ ;
+ TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6)
+ | (1<<WGM13) | (0<<WGM12) // phase-correct adjustable PWM (DS table 12-5)
+ ;
+
+ // set PWM resolution
+ PWM_TOP = PWM_TOP_INIT;
+
+ #if 0 // old 8-bit PWM setup
+ // configure PWM
+ // Setup PWM. F_pwm = F_clkio / 2 / N / TOP, where N = prescale factor, TOP = top of counter
+ // pre-scale for timer: N = 1
+ TCCR1A = (0<<WGM11) | (1<<WGM10) // 8-bit (TOP=0xFF) (DS table 12-5)
+ | (1<<COM1A1) | (0<<COM1A0) // PWM 1A in normal direction (DS table 12-4)
+ | (1<<COM1B1) | (0<<COM1B0) // PWM 1B in normal direction (DS table 12-4)
+ ;
+ TCCR1B = (0<<CS12) | (0<<CS11) | (1<<CS10) // clk/1 (no prescaling) (DS table 12-6)
+ | (0<<WGM13) | (0<<WGM12) // phase-correct PWM (DS table 12-5)
+ ;
+ #endif
+
+ // set up e-switch
+ SWITCH_PUE = (1 << SWITCH_PIN); // pull-up for e-switch
+ SWITCH_PCMSK = (1 << SWITCH_PCINT); // enable pin change interrupt
+}
+
+
+#define LAYOUT_DEFINED
+
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-28 12:01:40 +0000