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authorUri Shaked2019-11-20 18:39:23 +0200
committerUri Shaked2019-11-20 18:39:23 +0200
commit38d30d7de805fd25dd1fd130007868c53041a3de (patch)
tree154b168a2d03895c52dcc6bd85bb6c7be5d8feec
parentchore: rimraf dist before build (diff)
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feat: LAC, LAS, LAT, LDS instructions + tests
-rw-r--r--src/instruction.spec.ts48
-rw-r--r--src/instruction.ts22
2 files changed, 66 insertions, 4 deletions
diff --git a/src/instruction.spec.ts b/src/instruction.spec.ts
index d40ac3f..d37b67a 100644
--- a/src/instruction.spec.ts
+++ b/src/instruction.spec.ts
@@ -132,6 +132,45 @@ describe('avrInstruction', () => {
expect(cpu.cycles).toEqual(3);
});
+ it('should execute `LAC r19` instruction', () => {
+ loadProgram('3693');
+ cpu.data[19] = 0x02; // r19 <- 0x02
+ cpu.dataView.setUint16(30, 0x100, true); // Z <- 0x100
+ cpu.data[0x100] = 0x96;
+ avrInstruction(cpu);
+ expect(cpu.pc).toEqual(1);
+ expect(cpu.cycles).toEqual(1);
+ expect(cpu.data[19]).toEqual(0x96);
+ expect(cpu.dataView.getUint16(30, true)).toEqual(0x100);
+ expect(cpu.data[0x100]).toEqual(0x94);
+ });
+
+ it('should execute `LAS r17` instruction', () => {
+ loadProgram('1593');
+ cpu.data[17] = 0x11; // r17 <- 0x11
+ cpu.data[30] = 0x80; // Z <- 0x80
+ cpu.data[0x80] = 0x44;
+ avrInstruction(cpu);
+ expect(cpu.pc).toEqual(1);
+ expect(cpu.cycles).toEqual(1);
+ expect(cpu.data[17]).toEqual(0x44);
+ expect(cpu.data[30]).toEqual(0x80);
+ expect(cpu.data[0x80]).toEqual(0x55);
+ });
+
+ it('should execute `LAT r0` instruction', () => {
+ loadProgram('0792');
+ cpu.data[0] = 0x33; // r0 <- 0x33
+ cpu.data[30] = 0x80; // Z <- 0x80
+ cpu.data[0x80] = 0x66;
+ avrInstruction(cpu);
+ expect(cpu.pc).toEqual(1);
+ expect(cpu.cycles).toEqual(1);
+ expect(cpu.data[0]).toEqual(0x66);
+ expect(cpu.data[30]).toEqual(0x80);
+ expect(cpu.data[0x80]).toEqual(0x55);
+ });
+
it('should execute `LDI r28, 0xff` instruction', () => {
loadProgram('cfef');
avrInstruction(cpu);
@@ -140,6 +179,15 @@ describe('avrInstruction', () => {
expect(cpu.data[28]).toEqual(0xff);
});
+ it('should execute `LDS r5, 0x150` instruction', () => {
+ loadProgram('50905001');
+ cpu.data[0x150] = 0x7a;
+ avrInstruction(cpu);
+ expect(cpu.pc).toEqual(0x2);
+ expect(cpu.cycles).toEqual(2);
+ expect(cpu.data[5]).toEqual(0x7a);
+ });
+
it('should execute `LD r1, X` instruction', () => {
loadProgram('1c90');
cpu.data[0xc0] = 0x15;
diff --git a/src/instruction.ts b/src/instruction.ts
index dbb23e7..fe64f10 100644
--- a/src/instruction.ts
+++ b/src/instruction.ts
@@ -258,17 +258,28 @@ export function avrInstruction(cpu: ICPU) {
/* LAC, 1001 001r rrrr 0110 */
if ((opcode & 0xfe0f) === 0x9206) {
- /* not implemented */
+ const r = (opcode & 0x1f0) >> 4;
+ const clear = cpu.data[r];
+ const value = cpu.readData(cpu.dataView.getUint16(30, true));
+ cpu.writeData(cpu.dataView.getUint16(30, true), value & (255 - clear));
+ cpu.data[r] = value;
}
/* LAS, 1001 001r rrrr 0101 */
if ((opcode & 0xfe0f) === 0x9205) {
- /* not implemented */
+ const r = (opcode & 0x1f0) >> 4;
+ const set = cpu.data[r];
+ const value = cpu.readData(cpu.dataView.getUint16(30, true));
+ cpu.writeData(cpu.dataView.getUint16(30, true), value | set);
+ cpu.data[r] = value;
}
/* LAT, 1001 001r rrrr 0111 */
if ((opcode & 0xfe0f) === 0x9207) {
- /* not implemented */
+ const r = cpu.data[(opcode & 0x1f0) >> 4];
+ const R = cpu.readData(cpu.dataView.getUint16(30, true));
+ cpu.writeData(cpu.dataView.getUint16(30, true), r ^ R);
+ cpu.data[(opcode & 0x1f0) >> 4] = R;
}
/* LDI, 1110 KKKK dddd KKKK */
@@ -278,7 +289,10 @@ export function avrInstruction(cpu: ICPU) {
/* LDS, 1001 000d dddd 0000 kkkk kkkk kkkk kkkk */
if ((opcode & 0xfe0f) === 0x9000) {
- /* not implemented */
+ const value = cpu.readData(cpu.progMem[cpu.pc + 1]);
+ cpu.data[(opcode & 0x1f0) >> 4] = value;
+ cpu.pc++;
+ cpu.cycles++;
}
/* LDX, 1001 000d dddd 1100 */
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