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authorUri Shaked2020-07-09 16:09:44 +0300
committerUri Shaked2020-07-09 16:09:44 +0300
commit6ee7d2f247afe4ac30c0a42a58806956a0bedc69 (patch)
tree5212a3ada617ef7a5ced2d5cc899ae5b5ae2184c
parenttest(usart): extract constants (diff)
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fix(usart): TXC interrupt triggered incorrectly
close #51
-rw-r--r--src/peripherals/usart.spec.ts20
-rw-r--r--src/peripherals/usart.ts2
2 files changed, 18 insertions, 4 deletions
diff --git a/src/peripherals/usart.spec.ts b/src/peripherals/usart.spec.ts
index cda141d..2f976ec 100644
--- a/src/peripherals/usart.spec.ts
+++ b/src/peripherals/usart.spec.ts
@@ -23,6 +23,10 @@ const TXCIE = 0x40;
const TXC = 0x40;
const UDRE = 0x20;
+// Interrupt address
+const PC_INT_UDRE = 0x26;
+const PC_INT_TXC = 0x28;
+
describe('USART', () => {
it('should correctly calculate the baudRate from UBRR', () => {
const cpu = new CPU(new Uint16Array(1024));
@@ -103,23 +107,33 @@ describe('USART', () => {
cpu.writeData(0xc6, 0x61);
cpu.data[SREG] = 0x80; // SREG: I-------
usart.tick();
- expect(cpu.pc).toEqual(0x26);
+ expect(cpu.pc).toEqual(PC_INT_UDRE);
expect(cpu.cycles).toEqual(2);
expect(cpu.data[UCSR0A] & UDRE).toEqual(0);
});
- it('should trigger data tx complete interrupt if TXCIE is set', () => {
+ it('should trigger data TX Complete interrupt if TXCIE is set', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
cpu.writeData(UCSR0B, TXCIE | TXEN);
cpu.writeData(UDR0, 0x61);
cpu.data[SREG] = 0x80; // SREG: I-------
usart.tick();
- expect(cpu.pc).toEqual(0x28);
+ expect(cpu.pc).toEqual(PC_INT_TXC);
expect(cpu.cycles).toEqual(2);
expect(cpu.data[UCSR0A] & TXC).toEqual(0);
});
+ it('should not trigger data TX Complete interrupt if UDR was not written to', () => {
+ const cpu = new CPU(new Uint16Array(1024));
+ const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
+ cpu.writeData(UCSR0B, TXCIE | TXEN);
+ cpu.data[SREG] = 0x80; // SREG: I-------
+ usart.tick();
+ expect(cpu.pc).toEqual(0);
+ expect(cpu.cycles).toEqual(0);
+ });
+
it('should not trigger any interrupt if interrupts are disabled', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
diff --git a/src/peripherals/usart.ts b/src/peripherals/usart.ts
index c1d6f13..eb6171e 100644
--- a/src/peripherals/usart.ts
+++ b/src/peripherals/usart.ts
@@ -100,7 +100,7 @@ export class AVRUSART {
avrInterrupt(this.cpu, this.config.dataRegisterEmptyInterrupt);
this.cpu.data[this.config.UCSRA] &= ~UCSRA_UDRE;
}
- if (ucsrb & UCSRA_TXC && ucsrb & UCSRB_TXCIE) {
+ if (ucsra & UCSRA_TXC && ucsrb & UCSRB_TXCIE) {
avrInterrupt(this.cpu, this.config.txCompleteInterrupt);
this.cpu.data[this.config.UCSRA] &= ~UCSRA_TXC;
}
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