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authorUri Shaked2020-09-02 23:50:05 +0300
committerUri Shaked2020-09-02 23:50:05 +0300
commited81059fad8b84896467ec1438e37ab00fcdabbd (patch)
tree56306191ca824057b74d63d5bd211d9d4db35515
parentperf(timer): improve timer speed (diff)
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perf(timer): speed up interrupt handling
-rw-r--r--src/peripherals/timer.ts5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/peripherals/timer.ts b/src/peripherals/timer.ts
index dc1302a..5ba908e 100644
--- a/src/peripherals/timer.ts
+++ b/src/peripherals/timer.ts
@@ -232,6 +232,7 @@ export class AVRTimer {
private tcntUpdated = false;
private countingUp = true;
private divider = 0;
+ private pendingInterrupt = false;
// This is the temporary register used to access 16-bit registers (section 16.3 of the datasheet)
private highByteTemp: u8 = 0;
@@ -302,6 +303,7 @@ export class AVRTimer {
}
set TIFR(value: u8) {
+ this.pendingInterrupt = value > 0;
this.cpu.data[this.config.TIFR] = value;
}
@@ -367,7 +369,7 @@ export class AVRTimer {
}
}
this.tcntUpdated = false;
- if (this.cpu.interruptsEnabled) {
+ if (this.cpu.interruptsEnabled && this.pendingInterrupt) {
const { TIFR, TIMSK } = this;
if (TIFR & TOV && TIMSK & TOIE) {
avrInterrupt(this.cpu, this.config.ovfInterrupt);
@@ -381,6 +383,7 @@ export class AVRTimer {
avrInterrupt(this.cpu, this.config.compBInterrupt);
this.TIFR &= ~OCFB;
}
+ this.pendingInterrupt = false;
}
}
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