aboutsummaryrefslogtreecommitdiff
path: root/src/peripherals/timer.spec.ts
diff options
context:
space:
mode:
authorUri Shaked2020-04-04 16:22:32 +0300
committerUri Shaked2020-04-12 22:56:26 +0300
commit619652de465c0f3c73d867de3ec51c21f612b082 (patch)
tree64e87fbdd3d9ef3f100c50b8d0a02bd9aaca98ce /src/peripherals/timer.spec.ts
parentfeat(demo): add 16-bit timer (timer1) (diff)
downloadavr8js-619652de465c0f3c73d867de3ec51c21f612b082.tar.gz
avr8js-619652de465c0f3c73d867de3ec51c21f612b082.tar.bz2
avr8js-619652de465c0f3c73d867de3ec51c21f612b082.zip
feat(timer): implement 16-bit timers
e.g. Timer/Counter1 on ATmega328
Diffstat (limited to '')
-rw-r--r--src/peripherals/timer.spec.ts19
1 files changed, 18 insertions, 1 deletions
diff --git a/src/peripherals/timer.spec.ts b/src/peripherals/timer.spec.ts
index adcef04..7750f26 100644
--- a/src/peripherals/timer.spec.ts
+++ b/src/peripherals/timer.spec.ts
@@ -1,5 +1,5 @@
import { CPU } from '../cpu/cpu';
-import { AVRTimer, timer0Config, timer2Config } from './timer';
+import { AVRTimer, timer0Config, timer1Config, timer2Config } from './timer';
describe('timer', () => {
let cpu: CPU;
@@ -201,4 +201,21 @@ describe('timer', () => {
timer.tick();
expect(cpu.data[0xb2]).toEqual(2); // TCNT2 should be 2
});
+
+ describe('16 bit timers', () => {
+ it('should set OCF0A flag when timer equals OCRA (16 bit mode)', () => {
+ const timer = new AVRTimer(cpu, timer1Config);
+ cpu.writeData(0x84, 0xee); // TCNT1 <- 0x10ee
+ cpu.writeData(0x85, 0x10); // ...
+ cpu.writeData(0x88, 0xef); // OCR1A <- 0x10ef
+ cpu.writeData(0x89, 0x10); // ...
+ cpu.writeData(0x80, 0x0); // WGM1 <- 0 (Normal)
+ cpu.writeData(0x81, 0x1); // TCCR1B.CS <- 1
+ cpu.cycles = 1;
+ timer.tick();
+ expect(cpu.data[0x36]).toEqual(2); // TIFR0 should have OCF0A bit on
+ expect(cpu.pc).toEqual(0);
+ expect(cpu.cycles).toEqual(1);
+ });
+ });
});