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| author | Uri Shaked | 2020-12-09 00:51:13 +0200 |
|---|---|---|
| committer | Uri Shaked | 2020-12-09 00:51:58 +0200 |
| commit | 36c4134a26063248a2ef47f5ac8defe50d9476b1 (patch) | |
| tree | 44433290b0d684768216b33550a7af9a6fb4235f /src/peripherals/usart.spec.ts | |
| parent | test(cpu): improve test name (diff) | |
| download | avr8js-36c4134a26063248a2ef47f5ac8defe50d9476b1.tar.gz avr8js-36c4134a26063248a2ef47f5ac8defe50d9476b1.tar.bz2 avr8js-36c4134a26063248a2ef47f5ac8defe50d9476b1.zip | |
refactor: central interrupt handling #38
Diffstat (limited to 'src/peripherals/usart.spec.ts')
| -rw-r--r-- | src/peripherals/usart.spec.ts | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/peripherals/usart.spec.ts b/src/peripherals/usart.spec.ts index 2728f9c..c1e1570 100644 --- a/src/peripherals/usart.spec.ts +++ b/src/peripherals/usart.spec.ts @@ -150,6 +150,7 @@ describe('USART', () => { cpu.writeData(UCSR0B, UDRIE | TXEN); cpu.data[SREG] = 0x80; // SREG: I------- usart.tick(); + cpu.tick(); expect(cpu.pc).toEqual(PC_INT_UDRE); expect(cpu.cycles).toEqual(2); expect(cpu.data[UCSR0A] & UDRE).toEqual(0); @@ -163,6 +164,7 @@ describe('USART', () => { cpu.data[SREG] = 0x80; // SREG: I------- cpu.cycles = 1e6; usart.tick(); + cpu.tick(); expect(cpu.pc).toEqual(PC_INT_TXC); expect(cpu.cycles).toEqual(1e6 + 2); expect(cpu.data[UCSR0A] & TXC).toEqual(0); @@ -174,6 +176,7 @@ describe('USART', () => { cpu.writeData(UCSR0B, TXCIE | TXEN); cpu.data[SREG] = 0x80; // SREG: I------- usart.tick(); + cpu.tick(); expect(cpu.pc).toEqual(0); expect(cpu.cycles).toEqual(0); }); @@ -186,6 +189,7 @@ describe('USART', () => { cpu.data[SREG] = 0; // SREG: 0 (disable interrupts) cpu.cycles = 1e6; usart.tick(); + cpu.tick(); expect(cpu.pc).toEqual(0); expect(cpu.cycles).toEqual(1e6); expect(cpu.data[UCSR0A]).toEqual(TXC | UDRE); @@ -244,9 +248,11 @@ describe('USART', () => { cpu.writeData(UDR0, 0x48); // 'H' cpu.cycles += 16000; // 1ms usart.tick(); + cpu.tick(); expect(cpu.data[UCSR0A] & TXC).toEqual(0); cpu.cycles += 800; // 0.05ms usart.tick(); + cpu.tick(); expect(cpu.data[UCSR0A] & TXC).toEqual(TXC); }); }); |