aboutsummaryrefslogtreecommitdiff
path: root/src/peripherals
diff options
context:
space:
mode:
authorUri Shaked2020-07-09 16:02:15 +0300
committerUri Shaked2020-07-09 16:02:15 +0300
commit82082002e7ead64d3701359a776d9dd96eb92bac (patch)
tree3fd061c3da46d1b22a5d8db10205500953f4c308 /src/peripherals
parentchore: configure gitpod (#50) (diff)
downloadavr8js-82082002e7ead64d3701359a776d9dd96eb92bac.tar.gz
avr8js-82082002e7ead64d3701359a776d9dd96eb92bac.tar.bz2
avr8js-82082002e7ead64d3701359a776d9dd96eb92bac.zip
test(usart): extract constants
This makes the test code easier to read
Diffstat (limited to 'src/peripherals')
-rw-r--r--src/peripherals/usart.spec.ts117
1 files changed, 68 insertions, 49 deletions
diff --git a/src/peripherals/usart.spec.ts b/src/peripherals/usart.spec.ts
index d9843dc..cda141d 100644
--- a/src/peripherals/usart.spec.ts
+++ b/src/peripherals/usart.spec.ts
@@ -4,57 +4,76 @@ import { AVRUSART, usart0Config } from './usart';
const FREQ_16MHZ = 16e6;
const FREQ_11_0529MHZ = 11059200;
+// CPU registers
+const SREG = 95;
+
+// USART0 Registers
+const UCSR0A = 0xc0;
+const UCSR0B = 0xc1;
+const UCSR0C = 0xc3;
+const UBRR0L = 0xc4;
+const UBRR0H = 0xc5;
+const UDR0 = 0xc6;
+
+// Register bit names
+const U2X0 = 2;
+const TXEN = 8;
+const UDRIE = 0x20;
+const TXCIE = 0x40;
+const TXC = 0x40;
+const UDRE = 0x20;
+
describe('USART', () => {
it('should correctly calculate the baudRate from UBRR', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_11_0529MHZ);
- cpu.writeData(0xc5, 0); // UBRR0H <- 0
- cpu.writeData(0xc4, 5); // UBRR0L <- 5
+ cpu.writeData(UBRR0H, 0);
+ cpu.writeData(UBRR0L, 5);
expect(usart.baudRate).toEqual(115200);
});
it('should correctly calculate the baudRate from UBRR in double-speed mode', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc5, 3); // UBRR0H <- 3
- cpu.writeData(0xc4, 64); // UBRR0L <- 64
- cpu.writeData(0xc0, 2); // UCSR0A: U2X0
+ cpu.writeData(UBRR0H, 3);
+ cpu.writeData(UBRR0L, 64);
+ cpu.writeData(UCSR0A, U2X0);
expect(usart.baudRate).toEqual(2400);
});
it('should return 5-bits per byte when UCSZ = 0', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc0, 0);
+ cpu.writeData(UCSR0C, 0);
expect(usart.bitsPerChar).toEqual(5);
});
it('should return 6-bits per byte when UCSZ = 1', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc0, 0x2);
+ cpu.writeData(UCSR0A, 0x2);
expect(usart.bitsPerChar).toEqual(6);
});
it('should return 7-bits per byte when UCSZ = 2', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc0, 0x4);
+ cpu.writeData(UCSR0A, 0x4);
expect(usart.bitsPerChar).toEqual(7);
});
it('should return 8-bits per byte when UCSZ = 3', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc0, 0x6);
+ cpu.writeData(UCSR0A, 0x6);
expect(usart.bitsPerChar).toEqual(8);
});
it('should return 9-bits per byte when UCSZ = 7', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc0, 0x6);
- cpu.writeData(0xc1, 0x4);
+ cpu.writeData(UCSR0A, 0x6);
+ cpu.writeData(UCSR0B, 0x4);
expect(usart.bitsPerChar).toEqual(9);
});
@@ -62,55 +81,55 @@ describe('USART', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
usart.onByteTransmit = jest.fn();
- cpu.writeData(0xc1, 0x8); // UCSR0B <- TXEN
- cpu.writeData(0xc6, 0x61); // UDR0
+ cpu.writeData(UCSR0B, TXEN);
+ cpu.writeData(UDR0, 0x61);
expect(usart.onByteTransmit).toHaveBeenCalledWith(0x61);
});
it('should set UDRE and TXC flags after UDR0', () => {
const cpu = new CPU(new Uint16Array(1024));
new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc1, 0x8); // UCSR0B <- TXEN
- cpu.writeData(0xc0, 0); // UCSR0A <- 0
- cpu.writeData(0xc6, 0x61); // UDR0
- expect(cpu.data[0xc0]).toEqual(0x40 | 0x20); // UCSR0A: TXC | UDRE
+ cpu.writeData(UCSR0B, TXEN);
+ cpu.writeData(UCSR0A, 0);
+ cpu.writeData(UDR0, 0x61);
+ expect(cpu.data[UCSR0A]).toEqual(TXC | UDRE);
});
describe('tick()', () => {
it('should trigger data register empty interrupt if UDRE is set', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc1, 0x28); // UCSR0B <- UDRIE | TXEN
- cpu.writeData(0xc6, 0x61); // UDR0
- cpu.data[95] = 0x80; // SREG: I-------
+ cpu.writeData(UCSR0B, UDRIE | TXEN);
+ cpu.writeData(0xc6, 0x61);
+ cpu.data[SREG] = 0x80; // SREG: I-------
usart.tick();
expect(cpu.pc).toEqual(0x26);
expect(cpu.cycles).toEqual(2);
- expect(cpu.data[0xc0] & 0x20).toEqual(0); // UCSR0A should clear UDRE
+ expect(cpu.data[UCSR0A] & UDRE).toEqual(0);
});
it('should trigger data tx complete interrupt if TXCIE is set', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc1, 0x48); // UCSR0B <- TXCIE | TXEN
- cpu.writeData(0xc6, 0x61); // UDR0
- cpu.data[95] = 0x80; // SREG: I-------
+ cpu.writeData(UCSR0B, TXCIE | TXEN);
+ cpu.writeData(UDR0, 0x61);
+ cpu.data[SREG] = 0x80; // SREG: I-------
usart.tick();
expect(cpu.pc).toEqual(0x28);
expect(cpu.cycles).toEqual(2);
- expect(cpu.data[0xc0] & 0x40).toEqual(0); // UCSR0A should clear TXC
+ expect(cpu.data[UCSR0A] & TXC).toEqual(0);
});
it('should not trigger any interrupt if interrupts are disabled', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
- cpu.writeData(0xc1, 0x28); // UCSR0B <- UDRIE | TXEN
- cpu.writeData(0xc6, 0x61); // UDR0
- cpu.data[95] = 0; // SREG: 0 (disable interrupts)
+ cpu.writeData(UCSR0B, UDRIE | TXEN);
+ cpu.writeData(UDR0, 0x61);
+ cpu.data[SREG] = 0; // SREG: 0 (disable interrupts)
usart.tick();
expect(cpu.pc).toEqual(0);
expect(cpu.cycles).toEqual(0);
- expect(cpu.data[0xc0]).toEqual(0x40 | 0x20); // UCSR0A: TXC | UDRE
+ expect(cpu.data[UCSR0A]).toEqual(TXC | UDRE);
});
});
@@ -119,13 +138,13 @@ describe('USART', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
usart.onLineTransmit = jest.fn();
- cpu.writeData(0xc1, 0x8); // UCSR0B <- TXEN
- cpu.writeData(0xc6, 0x48); // 'H'
- cpu.writeData(0xc6, 0x65); // 'e'
- cpu.writeData(0xc6, 0x6c); // 'l'
- cpu.writeData(0xc6, 0x6c); // 'l'
- cpu.writeData(0xc6, 0x6f); // 'o'
- cpu.writeData(0xc6, 0xa); // '\n'
+ cpu.writeData(UCSR0B, TXEN);
+ cpu.writeData(UDR0, 0x48); // 'H'
+ cpu.writeData(UDR0, 0x65); // 'e'
+ cpu.writeData(UDR0, 0x6c); // 'l'
+ cpu.writeData(UDR0, 0x6c); // 'l'
+ cpu.writeData(UDR0, 0x6f); // 'o'
+ cpu.writeData(UDR0, 0xa); // '\n'
expect(usart.onLineTransmit).toHaveBeenCalledWith('Hello');
});
@@ -133,9 +152,9 @@ describe('USART', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
usart.onLineTransmit = jest.fn();
- cpu.writeData(0xc1, 0x8); // UCSR0B <- TXEN
- cpu.writeData(0xc6, 0x48); // 'H'
- cpu.writeData(0xc6, 0x69); // 'i'
+ cpu.writeData(UCSR0B, TXEN);
+ cpu.writeData(UDR0, 0x48); // 'H'
+ cpu.writeData(UDR0, 0x69); // 'i'
expect(usart.onLineTransmit).not.toHaveBeenCalled();
});
@@ -143,16 +162,16 @@ describe('USART', () => {
const cpu = new CPU(new Uint16Array(1024));
const usart = new AVRUSART(cpu, usart0Config, FREQ_16MHZ);
usart.onLineTransmit = jest.fn();
- cpu.writeData(0xc1, 0x8); // UCSR0B <- TXEN
- cpu.writeData(0xc6, 0x48); // 'H'
- cpu.writeData(0xc6, 0x69); // 'i'
- cpu.writeData(0xc6, 0xa); // '\n'
- cpu.writeData(0xc6, 0x74); // 't'
- cpu.writeData(0xc6, 0x68); // 'h'
- cpu.writeData(0xc6, 0x65); // 'e'
- cpu.writeData(0xc6, 0x72); // 'r'
- cpu.writeData(0xc6, 0x65); // 'e'
- cpu.writeData(0xc6, 0xa); // '\n'
+ cpu.writeData(UCSR0B, TXEN);
+ cpu.writeData(UDR0, 0x48); // 'H'
+ cpu.writeData(UDR0, 0x69); // 'i'
+ cpu.writeData(UDR0, 0xa); // '\n'
+ cpu.writeData(UDR0, 0x74); // 't'
+ cpu.writeData(UDR0, 0x68); // 'h'
+ cpu.writeData(UDR0, 0x65); // 'e'
+ cpu.writeData(UDR0, 0x72); // 'r'
+ cpu.writeData(UDR0, 0x65); // 'e'
+ cpu.writeData(UDR0, 0xa); // '\n'
expect(usart.onLineTransmit).toHaveBeenCalledWith('there');
});
});
If you find this content useful please consider a small donation via bitcoin: bitcoin:1mxKyQsHHugqRxPKgwaA7wUwJEGCNthn2?amount=0.001&message=Donation Scraping git contents via cgit is very resource intensive. The continued hosting of these git repositories is entirely financed by your bitcoin contributions. For donations of a least 1 mBTC you include your IP address in the message of your bitcoin donation. This will remove this message in the future for requests from your IP, which will significantly reduce token usage. In any case, any contributions to bitcoin address 1mxKyQsHHugqRxPKgwaA7wUwJEGCNthn2 are very welcome. Thanks in advance for you contribution to a self-sustaining ecosystem.