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* onBeforeInterrupt callbackavr32dd20Apexo2026-04-031-0/+7
* avr32dd20 compat, onSleep hookHEADmainApexo2026-03-283-30/+60
* style: organize importsUri Shaked2026-02-143-5/+4
* docs: add copyright notice to source codeUri Shaked2025-02-115-1/+16
* chore(deps): upgrade prettierUri Shaked2025-02-112-5/+8
* test: migrate tests from jest to vitestUri Shaked2025-02-113-1/+4
* chore(deps): upgrade typescript, jest, eslintUri Shaked2023-01-051-3/+3
* fix(cpu): don't clear RAM on reset #107Uri Shaked2022-04-301-1/+0
* style(instruction.spec): add comments for missing instruction tests and reord...Dudeplayz2022-02-071-33/+103
* test(instruction): add ADD, SUB and WDR unit testsDudeplayz2022-02-071-0/+54
* perf(cpu): speed up interruptsUri Shaked2022-01-201-11/+28
* fix(eeprom): EEPROM interrupt not firing #110Uri Shaked2021-10-241-2/+3
* refactor: remove the ICPU interfaceUri Shaked2021-09-103-33/+18
* feat(watchdog): implement watchdog timer #106Uri Shaked2021-09-102-1/+12
* fix(gpio): CBI/SBI handling in writes to PIN register #103Uri Shaked2021-09-072-6/+8
* feat(timer): external timer support #97Uri Shaked2021-08-151-2/+1
* feat(gpio): external interrupt/PCINT support (#82)Uri Shaked2021-07-071-0/+2
* perf(cpu): speed up event systemUri Shaked2021-06-201-25/+47
* feat(usart): implement RX #11Uri Shaked2021-02-191-1/+2
* perf(cpu): speed up event systemUri Shaked2020-12-122-18/+59
* test(cpu): fix implicit any errorUri Shaked2020-12-121-3/+5
* fix(cpu): event system issueUri Shaked2020-12-122-2/+63
* perf!: centeral timekeepingUri Shaked2020-12-091-1/+44
* refactor: central interrupt handling #38Uri Shaked2020-12-091-3/+76
* test(cpu): improve test nameUri Shaked2020-12-091-1/+1
* fix(cpu): incorrect address for RAMPZ / EINDUri Shaked2020-09-302-8/+8
* fix(interrupt): broken on ATmega2560Uri Shaked2020-09-022-1/+23
* fix(instruction): EICALL is brokenUri Shaked2020-09-022-1/+3
* test(instruction): extract constantsUri Shaked2020-06-041-238/+274
* feat(timer): Compare Match Output (#45)Uri Shaked2020-05-251-0/+4
* fix(timer): Reading TCNT in 2-cycle instructionsUri Shaked2020-04-291-12/+12
* fix(timer): incorrect high counter byte behaviorUri Shaked2020-04-281-0/+8
* fix(instruction): LD, ST instructions should take 2 clock cyclesUri Shaked2020-04-282-20/+33
* feat(instruction): 22-bit PC support #31Uri Shaked2020-04-093-20/+119
* feat(instruction): implement EICALL, EIJMP #31Uri Shaked2020-04-092-0/+38
* feat(instruction): implement ELPM #31Uri Shaked2020-04-082-0/+71
* test(instruction): use assembly in testsUri Shaked2020-04-021-89/+91
* refactor: added peripherals and cpu feature folderslironh2020-03-226-0/+1687
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