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* chore(deps): upgrade prettierUri Shaked2025-02-111-1/+4
* fix(timer): Phase Correct mode overruns #119Uri Shaked2022-03-221-2/+15
* fix(timer): OCRH masking #117Uri Shaked2022-02-211-3/+18
* fix(timer): setting TCNT doesn't update OCRA #111Uri Shaked2021-10-291-0/+8
* feat(timer): Force Output Compare (FOC) bitsUri Shaked2021-10-071-0/+34
* feat(timer): 3rd output compare (OCRnC) #96Uri Shaked2021-09-141-13/+96
* feat(timer): external timer support #97Uri Shaked2021-08-151-16/+50
* fix(timer): only set ICR hook for 16-bit timersUri Shaked2021-07-071-3/+3
* fix(timer): Timer1 PWM issues #94Uri Shaked2021-06-191-2/+2
* fix(timer): delay() is inaccurate #81Uri Shaked2020-12-291-8/+1
* fix(timer): Output Compare in PWM modes #78Uri Shaked2020-12-271-56/+110
* fix(timer): Overflow interrupt fires twice #80Uri Shaked2020-12-261-1/+5
* fix(timer): Output Compare sometimes misses Compare Match #79Uri Shaked2020-12-251-6/+14
* fix(timer): Output Compare issue #74Uri Shaked2020-12-211-4/+5
* fix(timer): TOV flag does not update correctly #75Uri Shaked2020-12-201-17/+21
* fix(timer): OCR values should be buffered #76Uri Shaked2020-12-201-6/+33
* fix(timer): Incorrect count when stopping a timerUri Shaked2020-12-121-14/+21
* perf!: centeral timekeepingUri Shaked2020-12-091-5/+25
* refactor: central interrupt handling #38Uri Shaked2020-12-091-36/+42
* feat: Support for simulating ATtinyx5 (e.g. ATtiny85) timers #64Uri Shaked2020-11-141-12/+33
* fix: AVRTimerConfig interface not exported #65Uri Shaked2020-11-141-1/+1
* perf(timer): speed up interrupt handlingUri Shaked2020-09-021-1/+4
* perf(timer): improve timer speedUri Shaked2020-09-021-2/+5
* fix(timer): keeps counting even when stopped #41Uri Shaked2020-08-011-0/+2
* perf(timer): improve tick() performanceUri Shaked2020-05-251-3/+4
* feat(timer): Compare Match Output (#45)Uri Shaked2020-05-251-32/+141
* fix(timer): stop Timer 2 when all CS bits are 0Uri Shaked2020-05-041-1/+1
* fix(timer): Reading TCNT in 2-cycle instructionsUri Shaked2020-04-291-0/+1
* fix(timer): incorrect high counter byte behaviorUri Shaked2020-04-281-23/+19
* style: reformat code with prettier 2.xUri Shaked2020-04-271-10/+10
* fix(timer): Timer value should not increment on the same cycle as TCNTn writeUri Shaked2020-04-271-2/+8
* test(timer): add more 16-bit timer testsUri Shaked2020-04-121-10/+10
* feat(timer): implement 16-bit timersUri Shaked2020-04-121-23/+130
* refactor: added peripherals and cpu feature folderslironh2020-03-221-0/+244