diff options
| author | Apexo | 2026-03-28 23:40:53 +0100 |
|---|---|---|
| committer | Apexo | 2026-03-28 23:40:53 +0100 |
| commit | 1b194ac4578dea8e71b0d61d1cb4d875f435ba71 (patch) | |
| tree | 786019a0c6f34b458f3272bf2ecbde0de1976e0a /src/peripherals/avrdx-rstctrl.ts | |
| download | anduril-sim-1b194ac4578dea8e71b0d61d1cb4d875f435ba71.tar.gz anduril-sim-1b194ac4578dea8e71b0d61d1cb4d875f435ba71.tar.bz2 anduril-sim-1b194ac4578dea8e71b0d61d1cb4d875f435ba71.zip | |
D3AA simulator
Diffstat (limited to 'src/peripherals/avrdx-rstctrl.ts')
| -rw-r--r-- | src/peripherals/avrdx-rstctrl.ts | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/peripherals/avrdx-rstctrl.ts b/src/peripherals/avrdx-rstctrl.ts new file mode 100644 index 0000000..370b9c3 --- /dev/null +++ b/src/peripherals/avrdx-rstctrl.ts @@ -0,0 +1,30 @@ +// AVR-Dx RSTCTRL - Reset Controller +// Handles software reset and reset flags. + +import { type CPU } from 'avr8js/cpu/cpu'; +import { type AVRDxCCP } from './avrdx-ccp'; + +export const RSTFR = 0; +export const SWRR = 1; +export const SWRST_bm = 0x01; + +export class AVRDxRSTCTRL { + /** Set this callback to handle software resets */ + onReset: (() => void) | null = null; + + constructor(cpu: CPU, base: number, ccp: AVRDxCCP) { + // RSTFR - reset flags, write 1 to clear + cpu.writeHooks[base + RSTFR] = (value) => { + cpu.data[base + RSTFR] &= ~value; + return true; + }; + + // SWRR - software reset register (CCP protected) + cpu.writeHooks[base + SWRR] = (value) => { + if (ccp.isUnlocked() && (value & SWRST_bm)) { + if (this.onReset) this.onReset(); + } + return true; + }; + } +} |
