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| author | Apexo | 2026-03-29 11:29:01 +0200 |
|---|---|---|
| committer | Apexo | 2026-03-29 11:29:01 +0200 |
| commit | 158116ad19455135b59929f4cdb569e55947ebbb (patch) | |
| tree | 7517d591d352a19069146b23633c691950fc5286 /src/peripherals | |
| parent | avr8js submodule (diff) | |
| download | anduril-sim-158116ad19455135b59929f4cdb569e55947ebbb.tar.gz anduril-sim-158116ad19455135b59929f4cdb569e55947ebbb.tar.bz2 anduril-sim-158116ad19455135b59929f4cdb569e55947ebbb.zip | |
cleanup exports
Diffstat (limited to 'src/peripherals')
| -rw-r--r-- | src/peripherals/avrdx-rstctrl.ts | 6 | ||||
| -rw-r--r-- | src/peripherals/avrdx-rtc-pit.ts | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/peripherals/avrdx-rstctrl.ts b/src/peripherals/avrdx-rstctrl.ts index 370b9c3..ce02552 100644 --- a/src/peripherals/avrdx-rstctrl.ts +++ b/src/peripherals/avrdx-rstctrl.ts @@ -4,9 +4,9 @@ import { type CPU } from 'avr8js/cpu/cpu'; import { type AVRDxCCP } from './avrdx-ccp'; -export const RSTFR = 0; -export const SWRR = 1; -export const SWRST_bm = 0x01; +const RSTFR = 0; +const SWRR = 1; +const SWRST_bm = 0x01; export class AVRDxRSTCTRL { /** Set this callback to handle software resets */ diff --git a/src/peripherals/avrdx-rtc-pit.ts b/src/peripherals/avrdx-rtc-pit.ts index 101f265..15feed0 100644 --- a/src/peripherals/avrdx-rtc-pit.ts +++ b/src/peripherals/avrdx-rtc-pit.ts @@ -16,7 +16,7 @@ const PERIOD_gm = 0x78; // bits [6:3] // PIT period to number of 32768Hz clock cycles // PERIOD field is bits [6:3] of CTRLA -export const PERIOD_CYCLES = [ +const PERIOD_CYCLES = [ 0, // 0x00: OFF 4, // 0x01: CYC4 8, // 0x02: CYC8 |