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| author | Selene ToyKeeper | 2020-03-13 18:04:43 -0600 |
|---|---|---|
| committer | Selene ToyKeeper | 2020-03-13 18:04:43 -0600 |
| commit | 51aae811654a3b73fa10ab449e22a11c858aa2d1 (patch) | |
| tree | 8bec4aa2d09e834918a9d7a3a89e134e62d9cf56 /hwdef-Emisar_D4v2.h | |
| parent | went back to continuous lowpass because it had the best noise reduction (diff) | |
| download | anduril-51aae811654a3b73fa10ab449e22a11c858aa2d1.tar.gz anduril-51aae811654a3b73fa10ab449e22a11c858aa2d1.tar.bz2 anduril-51aae811654a3b73fa10ab449e22a11c858aa2d1.zip | |
went back to slower clk/128 ADC timing
Diffstat (limited to 'hwdef-Emisar_D4v2.h')
| -rw-r--r-- | hwdef-Emisar_D4v2.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hwdef-Emisar_D4v2.h b/hwdef-Emisar_D4v2.h index addf429..60f3fae 100644 --- a/hwdef-Emisar_D4v2.h +++ b/hwdef-Emisar_D4v2.h @@ -48,7 +48,7 @@ #define PWM2_LVL OCR1B // OCR1B is the output compare register for PB1 -#define ADC_PRSCL 0x06 // clk/64 +#define ADC_PRSCL 0x07 // clk/128 // average drop across diode on this hardware #ifndef VOLTAGE_FUDGE_FACTOR |